COBHAM GR740 User Manual

GR740-UM-DS, Nov 2017, Version 1.7 48 www.cobham.com/gaisler
GR740
6 LEON4 - Fault-tolerant High-performance SPARC V8 32-bit Processor
6.1 Overview
LEON4 is a 32-bit processor core conforming to the IEEE-1754 (SPARC V8) architecture [SPARC]
with a subset of the V8E extensions [V8E]. It is designed for embedded applications, combining high
performance with low complexity and low power consumption.
The LEON4 core has the following main features: 7-stage pipeline with Harvard architecture, sepa-
rate instruction and data caches, hardware multiplier and divider, on-chip debug support and multi-
processor extensions.
The LEON4 processors in this device have fault-tolerance against SEU errors. The fault-tolerance is
focused on the protection of on-chip RAM blocks, which are used to implement IU/FPU register files
and the L1 cache memory.
6.1.1 Integer unit
The LEON4 integer unit is implemented according to the SPARC V8 manual [SPARC], including
hardware multiply and divide instructions. The number of register windows is eight. The pipeline
consists of 7 stages with a separate instruction and data cache interface.
6.1.2 Cache sub-system
LEON4 has a cache system consisting of a separate instruction and data cache. Both caches have
four ways, four KiB/way, and 32 bytes per line. The instruction cache maintains one valid bit per
cache line and uses streaming during line-refill to minimize refill latency. The data cache has one
valid bit per cache line, uses write-through policy and implements a double-word write-buffer. Bus-
snooping on the AHB bus maintains cache coherency for the data cache.
6.1.3 Floating-point unit and co-processor
The LEON4 integer unit provides interfaces for the high-performance GRFPU floating-point
unit.´The floating-point processor executes in parallel with the integer unit, and does not block the
operation unless a data or resource dependency exists. The floating-point controller and floating-point
unit are further describes in sections 7 and 8.
Integer pipeline
I-Cache D-Cache
4-Port Register File
AMBA AHB Master (128-bit)
AHB I/F
7-Stage
Interrupt controller
HW MUL/DIV
IEEE-754 FPU
Trace Buffer
Debug port
Interrupt port
Debug support unit
Figure 2. LEON4 processor core block diagram
SRMMU
DTLB
ITLB

COBHAM GR740 Specifications

General

Brand	COBHAM
Model	GR740
Category	Computer Hardware
Language	English