GR740-UM-DS, Nov 2017, Version 1.7 298 www.cobham.com/gaisler
GR740
Each timer can be configured to latch its value to a dedicated register when an event is detected on the
interrupt. All timers can be forced to reload when an event is detected on the interrupt bus. A dedi-
cated mask register is provided to filter the interrupts. See also section 5.9.
At reset, all timers are disabled except the watchdog timer on GPTIMER 0. The prescaler value and
reload registers are set to all ones, while the watchdog timer is set to 0xFFFF.
20.3 Registers
The cores are programmed through registers mapped into APB address space. The number of imple-
mented registers depend on the number of implemented timers.
Table 369.General Purpose Timer Unit registers
APB address offset Register
0x00 Scaler value register
0x04 Scaler reload value register
0x08 Configuration register
0x0C Timer latch configuration register
0x10 Timer 1 counter value register
0x14 Timer 1 reload value register
0x18 Timer 1 control register
0x1C Timer 1 latch register
0xn0Timer n counter value register
0xn4Timer n reload value register
0xn8Timer n control register
0xnCTimer n latch register
Table 370.0x00 - SCALER - Scaler value register
31 16 15 0
RESERVED SCALER
0 0xFFFF
rrw
31: 16 RESERVED
15: 0 Scaler value (SCALER)
Table 371.0x04 - SRELOAD- Scaler reload value register
31 16 15 0
RESERVED SRELOAD
0 0xFFFF
rrw
31: 16 RESERVED
15: 0 Scaler reload value (SRELOAD)
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