GR740-UM-DS, Nov 2017, Version 1.7 395 www.cobham.com/gaisler
GR740
33.6 DSU registers
33.6.1 DSU control register
Table 524. 0x000000- CTRL - DSU control register
31 1211109876543210
RESERVED PW HL PE EB EE DM BZ BX BS BW BE TE
0 000** **0***
r r rwwc r r r rwrwrwrwrwrw
31: 12 Reserved
11 Power down (PW) - Returns ‘1’ when processor is in power-down mode.
10 Processor halt (HL) - Returns ‘1’ on read when processor is halted. If the processor is in debug
mode, setting this bit will put the processor in halt mode.
9 Processor error mode (PE) - returns ‘1’ on read when processor is in error mode, else ‘0’. If written
with ‘1’, it will clear the error and halt mode.
8 External Break (EB) - Value of the external BREAK signal
7 External Enable (EE) - Value of the external DSU_EN signal
6 Debug mode (DM) - Indicates when the processor has entered debug mode.
5 Break on error traps (BZ) - if set, will force the processor into debug mode on all except the follow-
ing traps: priviledged_instruction, fpu_disabled, window_overflow, window_underflow, asynchro-
nous_interrupt, ticc_trap.
BZ is reset to the value of the external BREAK signal.
4 Break on trap (BX) - if set, will force the processor into debug mode when any trap occurs.
BX is reset to the value of the external BREAK signal.
3 Break on S/W breakpoint (BS) - if set, debug mode will be forced when an breakpoint instruction (ta
1) is executed.
2 Break on IU watchpoint (BW) - if set, debug mode will be forced on a IU watchpoint (trap 0xb).
BW is reset to the value of the external BREAK signal.
1 Break on error (BE) - if set, will force the processor to debug mode when the processor would have
entered error condition (trap in trap).
BE is reset to the value of the external BREAK signal.
0 Trace enable (TE) - Enables instruction tracing. If set the instructions will be stored in the trace
buffer. Remains set when then processor enters debug or error mode.
TE is reset to ’1’ when external signal BREAK=LOW, otherwise TE is reset to 0.
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