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General| Brand | COBHAM |
|---|---|
| Model | GR712RC |
| Category | Computer Hardware |
| Language | English |
Describes the manual's purpose and target audience, covering the GR712RC processor.
Outlines the key features and components of the GR712RC processor, including cores and memory.
Details the internal AHB/APB bus memory map and address ranges for various cores.
Specifies interrupt assignments and routing for the GR712RC peripherals.
Lists the GRLIB IP cores integrated into the GR712RC.
Lists external documents and resources for further information on GR712RC.
Lists known issues and errata found in the GR712RC, with descriptions and workarounds.
Provides a chronological list of changes made to the document across versions.
Describes the GR712RC package and the function of the I/O switch matrix for pin sharing.
Explains the generation and selection of the system clock for the processor and buses.
Describes the selectable clock source for SpaceWire interfaces.
Details clock requirements for the MIL-STD-1553B core.
Specifies clock frequency constraints for the telemetry input.
Outlines clock frequency constraints for the telecommand input.
Notes a proprietary function that is not supported.
Describes clocking requirements and division for the SLINK core.
Explains the SDRAM clock generation and phase tuning.
Lists cores connected to the clock gating unit for power saving.
Describes clocking behavior when the system is in test mode.
Introduces the LEON3FT processor cores, their architecture, and features.
Describes the LEON3 integer unit features, pipeline, and instructions.
Details the instruction and data caches configuration.
Explains the GRFPU floating-point unit and its capabilities.
Describes the SPARC V8 Memory Management Unit (SRMMU) functionality.
Details the LEON3 integer unit's main features and pipeline stages.
Provides an overview of the LEON3 integer unit.
Explains the 7-stage instruction pipeline of the LEON integer unit.
Details the SPARC implementor's identification and version registers.
Describes the support for SPARC V8 divide instructions.
Explains the SPARC integer multiply instructions.
Describes the Compare and Swap Alternative (CASA) instruction.
Details the hardware breakpoints functionality using %asr registers.
Describes the instruction trace buffer for storing executed instructions.
Explains the processor configuration register (%asr17) and its fields.
Details the exceptions handled by LEON3, including trap types and priorities.
Explains the SVT option for reducing code size for embedded applications.
Describes address space identifiers (ASI) and their usage for cache access.
Explains the processor power-down feature for minimizing power consumption.
Describes the processor reset operation and register reset values.
Details multi-processor support and cache coherency mechanisms.
Explains the cache sub-system architecture with separate I-cache and D-cache.
Describes the operation of the instruction cache, including misses and refills.
Describes the instruction cache operation, including refill and streaming.
Details the structure of an instruction cache tag entry.
Describes the data cache operation, write policy, and error handling.
Describes the data cache operation, including write-through policy.
Explains the write buffer functionality and potential exceptions.
Details the structure of a data cache tag entry.
Describes additional cache features like flushing and diagnostic access.
Describes cache flushing operations via FLUSH instruction or ASI writes.
Explains diagnostic access to cache tags and data using specific ASIs.
Describes data cache snooping for maintaining coherency with external memory.
Details the Cache Control Register (CCR) bits for cache operation.
Lists read-only cache configuration registers indicating size and features.
Explains how to access cache registers using LDA/STA instructions with ASI=2.
Provides software considerations for cache initialization after reset.
Describes the Memory Management Unit (MMU) and its interaction with caches.
Refers to table for MMU ASI mappings for different accesses.
Describes MMU/Cache operation and virtual to physical address translation.
Lists the implemented MMU registers.
Describes the TLB structure, size, and operation.
Details snoop tag diagnostic access for cache snooping.
Describes the GRFPU floating-point unit and its instruction timing.
Explains error detection and correction mechanisms for registers and caches.
Explains register file error protection (BCH, SEC/DED) and its impact.
Details the ASR16 register for IU register file error control.
Explains diagnostic read-out of register file checkbits.
Describes cache error protection mechanisms and counters.
Explains data scrubbing for cache and register files.
Describes initialization of register file check bits and caches.
Defines the ERRORN signal for processor error mode indication.
Provides an overview of the combined 8/32-bit memory controller.
Describes PROM read cycle waveforms, timing, and waitstates.
Describes memory-mapped IO access timing similar to PROM accesses.
Details SRAM access, read/write cycles, waitstates, and timing.
Explains 8-bit access configuration, EDAC, and RMW combinations.
Describes 8-bit I/O access behavior and byte access requirements.
Explains burst mode for memory bus bandwidth improvement.
Provides general information on SDRAM capabilities and supported devices.
Provides general information on SDRAM capabilities and supported devices.
Details SDRAM address mapping based on SRAM status.
Explains the SDRAM initialization sequence.
Describes programmable SDRAM timing parameters (TCAS, TRP, TRFC).
Explains the refresh function for SDRAM banks.
Discusses memory EDAC capabilities including BCH and Reed-Solomon.
Explains BCH EDAC, its equations, and usage.
Explains Reed-Solomon EDAC capabilities and coding schemes.
Describes EDAC error reporting mechanisms and AHB responses.
Explains bus ready signalling (BRDYN) for extending memory accesses.
Details external bus errors signaling via BEXCN.
Explains the READ output signal function for data bus direction.
Lists FTMCTRL memory controller registers mapped into APB address space.
Describes MCFG1 for programming ROM and IO timing.
Describes MCFG2 for controlling SRAM and SDRAM timing.
Describes MCFG3 for SDRAM refresh and EDAC control.
Describes MCFG4 for Reed-Solomon EDAC diagnostics.
Defines signals related to the memory controller.
Provides an overview of the 192 KiB on-chip RAM and its EDAC protection.
Describes the operation of the on-chip memory, including AHB access and EDAC.
Explains diagnostic access to EDAC checkbits using read/write bypass modes.
Details error reporting mechanisms including SEC counter and AHB status.
Lists FTAHBRAM configuration registers and their addresses.
Provides an overview of AHB status registers for monitoring error responses.
Describes how AHB status registers monitor transactions and store error information.
Lists AHB status registers and their APB addresses.
Provides an overview of the IRQMP multi-processor interrupt controller.
Describes the operation of the interrupt controller, including routing and prioritization.
Explains interrupt routing from peripherals to SPARC interrupts.
Describes the logic for interrupt prioritization based on levels and priority.
Lists the interrupt assignments for the GR712RC peripherals.
Explains how to monitor processor status (halted/running).
Details interrupt broadcasting functionality for multiprocessor systems.
Lists the registers for the interrupt controller.
Describes the interrupt level register for priority setting.
Details the interrupt pending register.
Describes the interrupt force register for processor 0.
Details the interrupt clear register.
Explains the multiprocessor status register.
Describes the processor interrupt mask register.
Details the broadcast register for interrupt propagation.
Describes the processor interrupt force register.
Explains the extended interrupt identification register.
Provides an overview of the Debug Support Unit (DSU) for debugging.
Describes the operation of the DSU and entry into debug mode.
Details the AHB trace buffer for storing AHB data transfers.
Describes the instruction trace buffer for storing executed instructions.
Details the DSU memory map and register addresses.
Describes the various DSU registers for control and configuration.
Describes the DSU control register bits for enabling features.
Details the break and single step register for controlling processor execution.
Explains the debug mode mask register for multiprocessor systems.
Describes the DSU trap register indicating trap types causing debug mode entry.
Explains the trace buffer time tag counter.
Details the DSU ASI register for diagnostic accesses.
Describes the AHB trace buffer control register.
Explains the AHB trace buffer index register for trace line tracking.
Details AHB trace buffer breakpoint registers for address matching.
Describes the instruction trace control register for pointer management.
Provides an overview of the JTAG debug interface for AHB bus access.
Describes the JTAG transmission protocol and data registers.
Explains the JTAG transmission protocol for AHB transfers.
States that the core does not implement AHB/APB registers for JTAG.
Describes the JTAG interface signals.
Provides an overview of the general purpose timer unit with prescaler and timers.
Describes the operation of the timer unit, including prescaler, timers, and watchdog.
Lists the registers for the GPTIMER unit.
Defines the timer unit signals, including wdogn.
Provides an overview of the timer unit with time latch capability.
Describes the operation, including prescaler, timers, and interrupt latching.
Lists the registers for the GRTIMER unit.
Explains the operation of the general purpose register for clock control.
Lists the general purpose register (GRGPREG) for clock generation.
Provides an overview of the two 32-bit GPIO ports and their functions.
Describes the operation of I/O ports, including buffers, interrupts, and polarity.
Lists the GPIO port registers and pin assignments.
Defines the GPIO signals and their functions.
Provides an overview of the six UART interfaces and their features.
Describes the operation of the UART, including transmitter and receiver.
Describes UART transmitter operation, data transfer, and frames.
Explains UART receiver operation, data sampling, and FIFO handling.
Describes baud-rate generation using a 12-bit down-counting scaler.
Details the UART loop back mode for testing transmitter and receiver.
Explains FIFO debug mode for accessing FIFO registers.
Describes UART interrupt generation for transmitter and receiver FIFOs.
Lists UART registers and their APB addresses.
Details the UART data register for read/write operations.
Explains the UART status register bits.
Describes the UART control register bits for enabling features.
Details the UART scaler reload register.
Explains the UART FIFO debug register.
Defines UART interface signals.
Provides an overview of the SpaceWire interface with RMAP support.
Describes the GRSPW operation, including link, AMBA, and RMAP interfaces.
Gives an overview of the GRSPW operation structure.
Explains SpaceWire protocol support, including RMAP and address checking.
Describes the SpaceWire link interface components.
Details the link interface Finite State Machine (FSM) control.
Describes the SpaceWire transmitter operation and control.
Explains the SpaceWire receiver operation and error detection.
Describes the time interface for sending and receiving time-codes.
Explains receiver DMA channels and packet reception flow.
Explains packet reception based on address matching and channel selection.
Describes basic channel functionality for packet storage.
Explains GRSPW setup for reception including registers.
Details descriptor table address setup for reception.
Explains how to enable descriptors for packet reception.
Describes DMA control register setup for reception.
Explains control bits affecting packet reception behavior.
Details status bits related to packet reception.
Explains error handling scenarios for packet reception.
Describes promiscuous mode for receiving all data regardless of address.
Explains transmitter DMA channels for data transmission.
Describes basic channel functionality for transmission.
Explains GRSPW setup for transmission including descriptor table.
Details enabling descriptors for transmission.
Explains how to start transmissions by setting the transmit enable bit.
Describes the transmission process including status updates.
Details the descriptor table address register for transmission.
Explains error handling for transmit operations (Abort Tx, AHB error, Link error).
Describes the Remote Memory Access Protocol (RMAP) fundamentals.
Describes RMAP protocol fundamentals, operations, and standards.
Details RMAP implementation within the GRSPW core.
Explains RMAP write commands and their restrictions.
Describes RMAP read commands and error handling.
Explains RMAP read-modify-write commands.
Details RMAP control options like enable bit and buffer disable.
Describes the AMBA interface including APB and AHB masters.
Describes the APB slave interface for accessing user registers.
Details the AHB master interface used by DMA engines.
Explains SpaceWire clock generation and selection.
Lists GRSPW core base addresses and interrupt numbers.
Defines the SpaceWire interface signals.
Provides an overview of the GRETH MAC, its interfaces, and speed support.
Describes the GRETH operation, including protocol and clocking.
Explains protocol support and limitations for the GRETH MAC.
Details clocking requirements for the Ethernet MAC.
Explains the transmitter DMA interface for Ethernet data transmission.
Details setting up a transmit descriptor for Ethernet packets.
Explains how to start Ethernet transmissions using DMA.
Describes descriptor handling after Ethernet packet transmission.
Explains how to set up data for Ethernet transmission.
Explains the receiver DMA interface for Ethernet data reception.
Details setting up reception descriptors for Ethernet packets.
Explains how to start Ethernet packet reception.
Describes descriptor handling after Ethernet packet reception.
Details reception behavior during AHB errors.
Explains the MDIO interface for PHY configuration and status.
Describes the RMII signals used for interfacing with external PHY.
Lists GRETH registers mapped into APB address space.
Defines the Ethernet interface signals.
Provides an overview of the two identical CAN-2.0 interfaces.
Explains the CAN controller based on Philips SJA1000.
Details the AHB interface for CAN, including addresses and interrupts.
Describes the BasicCAN mode operation.
Lists the BasicCAN register map allocation.
Describes the CAN control register bits.
Explains the CAN command register actions.
Details the CAN status register bits.
Explains the CAN interrupt register bits.
Describes the CAN transmit buffer layout.
Explains the CAN receive buffer layout.
Details the CAN acceptance filter modes and registers.
Describes the PeliCAN mode operation.
Lists the PeliCAN register map allocation.
Describes the CAN mode register bits.
Explains the CAN command register actions.
Details the CAN status register bits.
Explains the CAN interrupt register bits.
Describes the CAN interrupt enable register.
Details the arbitration lost capture register.
Explains the error code capture register.
Describes the error warning limit register.
Details the RX error counter.
Explains the TX error counter.
Describes the CAN transmit buffer layout for SFF and EFF frames.
Explains the CAN receive buffer layout for SFF and EFF frames.
Details the CAN acceptance filter modes and registers.
Explains the RX message counter register.
Lists common registers for CAN, including clock divider and bus timing.
Describes the clock divider register for mode selection.
Explains bus timing 0 parameters.
Describes bus timing 1 parameters.
Lists known differences between this CAN controller and SJA1000.
Defines the CAN interface signals.
Defines obsolete signals.
Provides an overview of the CAN bus multiplexor for core selection.
Describes the operation of the CAN bus multiplexor.
Lists the CAN multiplexor control registers.
Provides an overview of the MIL-STD-1553B interface.
Details the AHB interface for the MIL-STD-1553B core.
Explains 1553 clock generation and frequency requirements.
Lists B1553BRM registers and their AHB addresses.
Defines the MIL-STD-1553B interface signals.
Provides an overview of the I2C master core compatibility.
Describes the operation of the I2C master, including protocols and speeds.
Explains the I2C transmission protocol, START/STOP conditions.
Describes I2C clock generation using the prescale register.
Explains interrupts generated by the I2C master core.
Details the software operational model for I2C initialization and operation.
Lists the I2C-master registers mapped into APB address space.
Defines the I2C interface signals.
Provides an overview of the SPI controller and its interface.
Describes the SPI operation, including transmission protocol and clocking.
Explains SPI transmission protocol, including clock polarity and phase.
Describes SPI receive and transmit queues (FIFOs).
Explains SPI clock generation based on system clock and mode register.
Details master-only operation of the SPI controller.
Lists SPI controller registers mapped into APB address space.
Defines the SPI interface signals.
Provides an overview of the SLINK master core and its configuration.
Describes the SLINK operation, including transmission protocol and data transfers.
Explains SLINK transmission protocol and data transfer types.
Describes SLINK receive and transmit queues (FIFOs).
Explains SEQUENCE operations for SLINK data transfers.
Describes different transfer types for SLINK.
Explains parity calculation and error handling for SLINK.
Describes SLINK clock and SYNC generation.
Lists GRSLINK registers.
Defines the SLINK interface signals.
Provides an overview of the ASCS controller for serial link operations.
Describes the operation of the ASCS controller's serial and sync links.
Describes the ASCS serial link operation for TC/TM transfers.
Explains the synchronization link functionality for issuing pulses.
Lists GRASCS registers for command, control, and data.
Defines the ASCS interface signals.
Provides an overview of the GRTC Telecommand Decoder.
Explains the GRTC concept, hardware, and software split.
Details GRTC functions and programmable options.
Lists reference documents for telecommand data formats.
Lists reference documents for telecommand data formats.
Describes telecommand input protocol waveforms.
Explains the Coding Layer functionality, including synchronization and decoding.
Details synchronization and input channel selection logic.
Explains codeblock decoding using BCH code and error correction.
Describes the de-randomizer function for bit synchronization.
Explains the optional Non-Return-to-Zero Mark decoder.
Lists design specifics for the coding layer.
Explains the DMA interface for data transfer to the system buffer.
Describes data transmission from the Coding Layer to the system buffer.
Explains data formatting for telecommand codeblocks.
Shows the CLTU decoder state diagram with event handling.
Describes nominal data handling for candidate codeblocks.
Explains CASE 1 for telecommand reception handling.
Describes CASE 2 for telecommand reception handling.
Explains abandoned states and their handling.
Discusses buffer and FIFO relationships for data transfer.
Explains the buffer full condition and safety buffer mechanism.
Details the buffer full interrupt mechanism.
Explains the CLCW interface and its relationship with GRTM.
Describes the AMBA AHB slave interface constraints.
Explains numbering and naming conventions used in the document.
Explains numbering and naming conventions for CCSDS and AMBA interfaces.
Lists GRTC registers mapped into AHB I/O address space.
Lists interrupt registers for managing module interrupts.
Defines the GRTC interface signals.
Provides an overview of the GRTM Telemetry Encoder and its capabilities.
Lists CCSDS/ECSS/PSS documents relevant to the telemetry encoder.
Lists acronyms and abbreviations used in the document.
Introduces the layers implemented by the GRTM encoder.
Introduces the Data Link Layer, Sync/Coding, and Physical Layers.
Explains the Data Link Protocol Sub-layer functionality.
Details the Synchronization and Channel Coding Sub-Layer functions.
Explains the Physical Layer functionality.
Describes the Data Link Protocol Sub-Layer configuration.
Describes Physical Channel configuration parameters.
Explains Virtual Channel Frame Service using DMA.
Describes Virtual Channel Generation for Idle Frames.
Explains Virtual Channel Multiplexing functionality.
Details Master Channel Generation.
Explains Master Channel Frame Service.
Describes Master Channel Multiplexing.
Explains All Frame Generation functionality.
Describes synchronization and channel coding functions.
Describes the Attached Synchronization Marker.
Explains the Reed-Solomon Encoder capabilities and codes.
Describes the Pseudo-Randomiser function.
Explains the Convolutional Encoder schemes.
Describes the Physical Layer functions.
Describes the NRZ-Mark encoder.
Explains the Split-Phase Level modulator.
Describes the Sub-Carrier modulator.
Explains the Clock Divider function for telemetry/channel encoding.
Describes the connectivity of encoders and modulators.
Introduces the DMA interface operation for Transfer Frames.
Introduces the DMA interface operation for Transfer Frames.
Explains descriptor setup for DMA transmission.
Describes how to start transmissions using DMA.
Explains descriptor handling after transmission.
Details interrupts related to DMA and telemetry transmission.
Lists GRTM DMA registers.
Provides an overview of the clock gating unit for power saving.
Describes the operation of the clock gating unit for enabling/disabling clocks.
Lists clock unit control registers.
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