COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 65 www.cobham.com/gaisler
GR712RC
cycle from when BRDYN is first asserted until it is visible internally. In figure 28, one cycle is added
to the data2 phase.
If burst accesses and BRDYN signaling are to be used together, special care needs to be taken to make
sure BRDYN is raised between the separate accesses of the burst. The controller does not raise the
select and OEN signals (in the read case) between accesses during the burst so if BRDYN is kept
asserted until the select signal is raised, all remaining accesses in the burst will finish with just the
configured fixed number of wait states.
5.12 External bus errors
An access error on the external memory bus can be signalled by asserting the BEXCN signal for read
and write accesses. For reads it is sampled together with the read data. For writes it is sampled on the
last rising edge before chip select is de-asserted, which is controlled by means of waitstates or bus
ready signalling. If the usage of BEXCN is enabled in memory configuration register 1, an error
response will be generated on the internal AHB bus. BEXCN can be enabled or disabled through
memory configuration register 1, and is active for all areas (PROM, IO and RAM). BEXCN is only
sampled in the last access for 8-bit mode for RAM and PROM. That is, when four bytes are written
for a word access to 8-bit wide memory BEXCN is only sampled in the last access with the same tim-
ing as a single access in 32-bit mode.
Figure 28. BRDYN (asynchronous) sampling and BEXCN timing. Lead-out cycle is only applicable for I/O-accesses.
data1 data2
address
romsn/iosn
data
oen
data2 lead-out
sdclk
D1
A1
brdyn
bexcn
Figure 29. Read cycle with one waitstate (configured) and one BRDYN generated waitstate (synchronous sampling).
data1 data2
address
romsn/iosn
data
oen
data2 lead-out
sdclk
D1
A1
brdyn
data2
ws
brdyn

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English