GR712RC-UM, Jun 2017, Version 2.9 191 www.cobham.com/gaisler
GR712RC
26.4.4 CASE 1
When an Event 4 – (E4): CODEBLOCK REJECTION – occurs for any of the 37 possible “Candidate
Codeblocks” that can follow Codeblock 0 (possibly the tail sequence), the decoder returns to the
SEARCH state (S2), with the following actions:
• The codeblock is abandoned (erased)
• No information octets are transferred to the remote ring buffer
• An “End of Candidate Frame” flag is written, indicating the end of the transfer of a block of
octets that make up a “Candidate Frame”.
26.4.5 CASE 2
When an Event 2 – (E2): CHANNEL DEACTIVATION – occurs which affects any of the 37 possible
“Candidate Codeblocks” that can follow Codeblock 0, the decoder returns to the INACTIVE state
(S1), with the following actions:
• The codeblock is abandoned (erased)
• No information octets are transferred to the remote ring buffer
• An “End of Candidate Frame” flag is written, indicating the end of the transfer of a block of
octets that make up a “Candidate Frame”
26.4.6 Abandoned
• B: When an Event 4 (E4), or an Event 2 (E2), occurs which affects the first candidate codeblock
0, the CLTU shall be abandoned. No candidate frame octets have been transferred.
• C: If and when more than 37 Codeblocks have been accepted in one CLTU, the decoder returns
to the SEARCH state (S2). The CLTU is effectively aborted and this is will be reported to the
software by writing the “Candidate Frame Abandoned flag” to bit 1 or 17, indicating to the soft-
ware to erase the “Candidate frame”.
26.5 Relationship between buffers and FIFOs
The conversion from the peripheral data width (8 bit for the coding layer receiver), to 32 bit system
word width, is done in the peripheral FIFO.
All access towards the system ring buffer are 32-bit aligned. When the amount of received bytes is
odd or not 32-bit aligned, the FIFO will keep track of this and automatically solve this problem. For
the reception data path, the 32 bit aligned accesses could result in incomplete words being written to
the ring buffer. This means that some bytes aren’t correct (because not yet received), but this is no
problem due to the fact that the hardware write pointer (rx_w_ptr) always points to the last, correct,
data byte.
The local FIFO ensures that DMA transfer on the AMBA AHB bus can be made by means of 2-word
bursts. If the FIFO is not yet filled and no new data is being received this shall generate a combination
of single accesses to the AMBA AHB bus if the last access was indicating an end of frame or an aban-
doned frame.
If the last single access is not 32-bit aligned, this shall generate a 32-bit access anyhow, but the
receive-write-pointer shall only be incremented with the correct number of bytes. Also in case the pre-
vious access was not 32-bit aligned, then the start address to write to will also not be 32-bit aligned.
Here the previous 32-bit access will be repeated including the bytes that were previously missing, in
order to fill-up the 32-bit remote memory-controller without gaps between the bytes.
The receive-write-pointer shall be incremented according to the number of bytes being written to the
remote memory controller.
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