COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 91 www.cobham.com/gaisler
GR712RC
12.3 Registers
The core is programmed through registers mapped at address 0x80100600.
Table 56. GRTIMER unit registers
APB address Register Reset value
0x80100600 Scaler value 0x000000FF
0x80100604 Scaler reload value 0x000000FF
0x80100608 Configuration register 0x0000000A
0x8010060C Timer latch configuration register 0x00000000
0x80100610 Timer 1 counter value register -
0x80100614 Timer 1 reload value register -
0x80100618 Timer 1 control register IE=0, EN=0
0x8010061C Timer 1 latch register -
0x80100620 Timer 2 counter value register -
0x80100624 Timer 2 reload value register -
0x80100628 Timer 2 control register IE=0, EN=0
0x8010062C Timer 2 latch register -
Table 57. Scaler value
31 87 0
“000..0” SCALER VALUE
31: 8 Reserved. Always reads as ‘000...0’
7: 0 Scaler value
Table 58. Scaler reload value
31 87 0
“000..0” SCALER RELOAD VALUE
31: 8 Reserved. Always reads as ‘000...0’
7: 0 Scaler reload value
Table 59. GRTIMER Configuration register
31 12 11 10 9 8 7 3 2 0
“000..0” EL “0” DF SI IRQ TIMERS
31: 12 Reserved. Always reads as ‘000...0’
11 Enable latching (EL). If set, on the next matching interrupt, the latches will be loaded with the corre-
sponding timer values. The bit is then automatically cleared, not to load a timer value until set again.
10 Reserved. Always reads as ‘0’
9 Disable timer freeze (DF). If set the timer unit can not be freezed, otherwise timers will halt when
the processor enters debug mode.
8 Separate interrupts (SI). Set to 0 to indicate common interrupt (7) for each timer. Read-only.
7: 3 Interrupt ID of first timer. Set to 7. Read-only.
2: 0 Number of implemented timers. Set to 2. Read-only.
Table 60. Timer latch configuration register
31 0
SELECT

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English