GR712RC-UM, Jun 2017, Version 2.9 92 www.cobham.com/gaisler
GR712RC
31: 0 Specifies what bits of the AMBA interrupt shall cause the Timer Latch Register to latch the timer
values. Bit 31 - 1 indicates interrupts 31 - 1
Table 61. Timer counter value registers
31 0
TIMER COUNTER VALUE
31: 0 Timer Counter value. Decremented by 1 for each prescaler tick.
Table 62. Timer reload value registers
31 0
TIMER RELOAD VALUE
31: 0 Timer Reload value. This value is loaded into the timer counter value register when ‘1’ is written to
load bit in the timers control register.
Table 63. Timer control registers
31 76543210
“000..0” DH CH IP IE LD RS EN
31: 7 Reserved. Always reads as ‘000...0’
6 Debug Halt (DH): Value of GPTI.DHALT signal which is used to freeze counters (e.g. when a sys-
tem is in debug mode). Read-only.
5 Chain (CH): Chain with preceding timer. If set for timer n, decrementing timer n begins when timer
(n-1) underflows.
4 Interrupt Pending (IP): Sets when an interrupt is signalled. Remains ‘1’ until cleared by writing ‘0’
to this bit.
3 Interrupt Enable (IE): If set the timer signals interrupt when it underflows.
2 Load (LD): Load value from the timer reload register to the timer counter value register.
1 Restart (RS): If set the value from the timer reload register is loaded to the timer counter value regis-
ter and decrementing the timer is restarted.
0 Enable (EN): Enable the timer.
Table 64. Timer latch registers
31 0
LTCV
31: 0 Latched Timer Counter Value (LTCV). Value latch from corresponding timer.
Table 60. Timer latch configuration register
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