GR712RC-UM, Jun 2017, Version 2.9 165 www.cobham.com/gaisler
GR712RC
22.4 Signal definitions
The signals are described in table 171.
7 Receive acknowledge (RxACK) - Received acknowledge from slave. ‘1’ when no acknowledge is
received, ‘0’ when slave has acknowledged the transfer.
6
I
2
C-bus busy (BUSY) - This bit is set to ‘1’ when a start signal is detected and reset to ‘0’ when a
stop signal is detected.
5 Arbitration lost (AL) - Set to ‘1’ when the core has lost arbitration. This happens when a stop signal
is detected but not requested or when the master drives I2CSDA high but I2CSDA is low.
4:2 RESERVED
1 Transfer in progress (TIP) - ‘1’ when transferring data and ‘0’ when the transfer is complete. This bit
is also set when the core will generate a STOP condition.
0 Interrupt flag (IF) - This bit is set when a byte transfer has been completed and when arbitration is
lost. If IEN in the control register is set an interrupt will be generated. New interrupts will be gener-
ated even if this bit has not been cleared.
Table 171.Signal definitions
Signal name Type Function Active
I2CSCL Input/Output
I
2
C clock line
-
I2CSDA Input/Output
I
2
C data line
-
Table 170. I
2
C-master status register
To Next Page
Loading...
Need help?
General
