GR712RC-UM, Jun 2017, Version 2.9 99 www.cobham.com/gaisler
GR712RC
set in the UART status register. Transmission resumes and the TS is cleared when a new character is
loaded into the transmitter FIFO. When the FIFO is empty the TE bit is set in the status register. If the
transmitter is disabled, it will immediately stop any active transmissions including the character cur-
rently being shifted out from the transmitter shift register. The transmitter holding register may not be
loaded when the transmitter is disabled or when the FIFO (or holding register) is full. If this is done,
data might be overwritten and one or more frames are lost.
The TF status bit (not to be confused with the TF control bit) is set if the transmitter FIFO is currently
full and the TH bit is set as long as the FIFO is less than half-full (less than half of entries in the FIFO
contain data). The TF control bit enables FIFO interrupts when set. The status register also contains a
counter (TCNT) showing the current number of data entries in the FIFO.
15.2.2 Receiver operation
The receiver is enabled for data reception through the receiver enable (RE) bit in the UART control
register. The receiver looks for a high to low transition of a start bit on the receiver serial data input
pin. If a transition is detected, the state of the serial input is sampled a half bit clocks later. If the serial
input is sampled high the start bit is invalid and the search for a valid start bit continues. If the serial
input is still low, a valid start bit is assumed and the receiver continues to sample the serial input at
one bit time intervals (at the theoretical centre of the bit) until the proper number of data bits and the
parity bit have been assembled and one stop bit has been detected. The serial input is shifted through
an 8-bit shift register where all bits have to have the same value before the new value is taken into
account, effectively forming a low-pass filter with a cut-off frequency of 1/8 system clock.
The receiver also has a configurable FIFO which is identical to the one in the transmitter. As men-
tioned in the transmitter part, both the holding register and FIFO will be referred to as FIFO.
During reception, the least significant bit is received first. The data is then transferred to the receiver
FIFO and the data ready (DR) bit is set in the UART status register as soon as the FIFO contains at
least one data frame. The parity, framing and overrun error bits are set at the received byte boundary,
at the same time as the data ready would have been set. The data frame is not stored in the FIFO if an
error is detected. Also, the new error status bits are or:ed with the old values before they are stored
into the status register. Thus, they are not cleared until written to with zeros from the AMBA APB
bus. If both the receiver FIFO and shift registers are full when a new start bit is detected, then the
character held in the receiver shift register will be lost and the overrun bit will be set in the UART sta-
tus register.
The RF status bit (not to be confused with the RF control bit) is set when the receiver FIFO is full.
The RH status bit is set when the receiver FIFO is half-full (at least half of the entries in the FIFO con-
tain data frames). The RF control bit enables receiver FIFO interrupts when set. A RCNT field is also
available showing the current number of data frames in the FIFO.
15.3 Baud-rate generation
Each UART contains a 12-bit down-counting scaler to generate the desired baud-rate. The scaler is
clocked by the system clock and generates a UART tick each time it underflows. It is reloaded with
the value of the UART scaler reload register after each underflow. The resulting UART tick frequency
should be 8 times the desired baud-rate.
The scalear reload value is calculated as follows (where F
CLK
is the sytem clock frequency):
SCALER_RELOAD_VALUE = F
CLK
/ (BAUD_RATE * 8) - 1
15.4 Loop back mode
If the LB bit in the UART control register is set, the UART will be in loop back mode. In this mode,
the transmitter output is internally connected to the receiver input. It is then possible to perform loop
back tests to verify operation of receiver, transmitter and associated software routines. In this mode,
the outputs remain in the inactive state, in order to avoid sending out data.
To Next Page
Loading...
Need help?
General
