COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 62 www.cobham.com/gaisler
GR712RC
5.10 Memory EDAC
The memory controller contains two separate EDACs, a BCH-based for all memory types and a Reed-
Solomon based for SDRAM only.
SDRAM is possible to use on both banks in 32-bit mode with EDAC.
Both SRAM and PROM are possible to use on both banks in 32-bit mode with or without EDAC.
Both SRAM and PROM are possible to use on both banks in 8-bit mode without EDAC.
Both SRAM and PROM are possible to use only on the first bank in 8-bit mode with EDAC under
certain circumstances. When only two PROM banks are used, there is no limitation on how large the
memory device size can be that is located in a bank, provided that the memory device size is equal or
less than the bank size itself. See section 1.7.7 for details.
5.10.1 BCH EDAC
The FTMCTRL is provided with an BCH EDAC that can correct one error and detect two errors in a
32-bit word. For each word, a 7-bit checksum is generated according to the equations below. A cor-
rectable error will be handled transparently by the memory controller, but adding one waitstate to the
access. If an un-correctable error (double-error) is detected, the current AHB cycle will end with an
error response. The EDAC can be used during access to PROM, SRAM and SDRAM areas by setting
the corresponding EDAC enable bits in the MCFG3 register. The equations below show how the
EDAC checkbits are generated (where Dn corresponds to DATA[n]:
CB[0]=D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31
CB[1]=D0
^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28
CB
[2]=D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31
CB
[3]=D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29
CB[4]=D2
^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31
CB[5]=D8
^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30^ D31
CB[6]=D0
^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31
If the SRAM is configured in 8-bit mode, the EDAC checkbit bus (CB[7:0]) is not used but it is still
possible to use EDAC protection. Data is always accessed as words (4 bytes at a time) and the corre-
sponding checkbits are located at the address acquired by inverting the word address (bits 2 to 27) and
using it as a byte address. The same chip-select is kept active. A word written as four bytes to
addresses 0, 1, 2, 3 will have its checkbits at address 0xFFFFFFF, addresses 4, 5, 6, 7 at 0xFFFFFFE
and so on. All the bits up to the maximum bank size will be inverted while the same chip-select is
always asserted. This way all the bank sizes can be supported and no memory will be unused (except
for a maximum of 4 byte in the gap between the data and checkbit area). A read access will automati-
cally read the four data bytes individually from the nominal addresses and the EDAC checkbit byte
from the top part of the bank. A write cycle is performed the same way. Byte or half-word write
accesses will result in an automatic read-modify-write access where 4 data bytes and the checkbit byte
are firstly read, and then 4 data bytes and the newly calculated checkbit byte are writen back to the
memory. This 8-bit mode applies to SRAM while SDRAM always uses 32-bit accesses. The size of
the memory bank is determined from the settings in MCFG2.
If the ROM is configured in 8-bit mode, EDAC protection is provided in a similar way as for the
SRAM memory described above. The difference is that write accesses are not being handled automat-
ically. Instead, write accesses must only be performed as individual byte accesses by the software,
writing one byte at a time, and the corresponding checkbit byte must be calculated and be written to
the correct location by the software.
The operation of the EDAC can be tested trough the MCFG3 register. If the WB (write bypass) bit is
set, the value in the TCB field will replace the normal checkbits during memory write cycles. If the
RB (read bypass) is set, the memory checkbits of the loaded data will be stored in the TCB field
during memory read cycles. NOTE: when the EDAC is enabled, the RMW bit in memory configura-
tion register 2 must be set.

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English