GR712RC-UM, Jun 2017, Version 2.9 61 www.cobham.com/gaisler
GR712RC
grammed in the refresh counter reload field in the MCFG3 register. Depending on SDRAM type, the
required period is typically 7.8 or 15.6 s (corresponding to 780 or 1560 clocks at 100 MHz). The
generated refresh period is calculated as (reload value+1)/sysclk. The refresh function is enabled by
setting bit 31 in MCFG2.
5.9.1 SDRAM commands
The controller can issue three SDRAM commands by writing to the SDRAM command field in
MCFG2: PRE-CHARGE, AUTO-REFRESH and LOAD-MODE-REG (LMR). If the LMR command
is issued, the CAS delay as programmed in MCFG2 will be used. Remaining fields are fixed: 8-word
sequential read burst, single location write. The command field will be cleared after a command has
been executed. When changing the value of the CAS delay, a LOAD-MODE-REGISTER command
should be generated at the same time. NOTE: when issuing SDRAM commands, the SDRAM refresh
must be disabled.
5.9.2 Read and write cycles
A read cycle is started by performing an ACTIVATE command to the desired bank and row, followed
by a READ command after the programmed CAS delay. A read burst is performed if a burst access
has been requested on the AHB bus. The read cycle is terminated with a PRE-CHARGE command,
no banks are left open between two accesses.
Write cycles are performed similarly to read cycles, with the difference that WRITE commands are
issued after activation. A write burst on the AHB bus will generate a burst of write commands without
idle cycles in-between.
5.9.3 Read-modify-write cycles
If EDAC is enabled and a byte or half-word write is performed, the controller will perform a read-
modify-write cycle to update the checkbits correctly. This is done by performing an ACTIVATE com-
mand, followed by READ, WRITE and PRE-CHARGE. The write command interrupts the read burst
and the data mask signals will be raised two cycles before this happens as required by the SDRAM
standard.
5.9.4 Address bus
The address bus of the SDRAM devices should be connected to ADDRESS[14:2], the bank address to
ADDRESS[16:15]. The MSB part of ADDRESS[14:2] can be left unconnected if not used.
5.9.5 Initialisation
Each time the SDRAM is enabled (bit 14 in MCFG2), an SDRAM initialisation sequence will be sent
to both SDRAM banks. The sequence consists of one PRECHARGE, eight AUTO-REFRESH and
one LOAD-COMMAND-REGISTER command.
To Next Page
Loading...
Need help?
General
