GR712RC-UM, Jun 2017, Version 2.9 158 www.cobham.com/gaisler
GR712RC
21.4 Registers
The core is programmed through registers mapped into AHB I/O address space. The internal registers
of Core1553BRM are mapped on the 33 lowest AHB addresses. These addresses are 32-bit word
aligned although only the lowest 16 bits are used. Refer to the Actel Core1553BRM MIL-STD-1553
BC, RT, and MT data sheet for detailed information.
B1553BRM status/control register
13 Bus reset. If set a bus reset mode code has been received. Generates an irq when set.
12 Reset. For asynchronous toplevel only. Software reset. Self clearing.
11:9 Reserved.
8:5 Reserved.
4: Address error. Shows the value of the rtaderr output from Core1553BRM.
3: Memory failure. Shows the value of the memfail output from Core1553BRM.
2: Busy. Shows the value of the busy output from Core1553BRM.
1: Active. Show the value of the active output from Core1553BRM.
0: Ssyfn. Connects directly to the ssyfn input of the Core1553BRM core. Resets to 0.
Note: Ssyfn is reset to ‘0’, which causes the BRM to set the subsystem flag bit in the status words sent
out.
B1553BRM interrupt register
2: Message interrupt acknowledge. Controls the intackm input signal of the Core1553BRM core.
1: Hardware interrupt acknowledge. Controls the intackh input signal of the Core1553BRM core.
0: Interrupt level. Controls the intlevel input signal of the Core1553BRM core.
AHB page address register
[31:17]: Holds the top most bits of the AHB address of the allocated memory area.
Table 162.B1553BRM registers
AHB address Register
0x0xFFF00000 - 0xFFF00084 Core1553BRM registers
0xFFF00100 B1553BRM status/control
0xFFF00104 B1553BRM interrupt settings
0xFFF00108 AHB page address register
Figure 68. B1553BRM status/control register
0
1
3
31
RESERVED
ssysfn
active
busy
memfailrtaderr
2
4
RESRESreset
5
8
9
11
12
1314
busrst
Figure 69. B1553RM interrupt register
0
1
31
RESERVED
intlevel
intackh
intackm
2
Figure 70. AHB page address register
031
RESERVED
ahbaddr
abits