GR712RC-UM, Jun 2017, Version 2.9 188 www.cobham.com/gaisler
GR712RC
26.3.6 Direct Memory Access (DMA)
This interface provides Direct Memory Access (DMA) capability between the AMBA bus and the
Coding Layer. The DMA operation is programmed via an AHB slave interface.
The DMA interface is an element in a communication concept that contains several levels of buffer-
ing. The first level is performed in the Coding Layer where a complete codeblock is received and kept
until it can be corrected and sent to the next level of the decoding chain. This is done by inserting each
correct information octet of the codeblock in an on-chip local First-In-First-Out (FIFO) memory
which is used for providing improved burst capabilities. The data is then transferred from the FIFO to
a system level ring buffer in the user memory which is accessed by means of DMA.
The following storage elements can thus be found in this design:
The shift and hold registers in the Coding Layer
The local FIFO (parallel; 32-bit; 4 words deep)
The system ring buffer (external memory; 32-bit; 1 to 256 KiB deep).
26.4 Transmission
The transmission of data from the Coding Layer to the system buffer is described hereafter.
The serial data is received and shifted in a shift register in the Coding Layer when the reception is
enabled. After correction, the information content of the shift register is put into a hold register.
When space is available in the peripheral FIFO, the content of the hold register is transferred to the
FIFO. The FIFO is of 32-bit width and the byte must thus be placed on the next free byte location in
the word.
When the FIFO is filled for 50%, a request is done to transfer the available data towards the system
level buffer.
If the system level ring buffer isn’t full, the data is transported from the FIFO, via the AHB master
interface towards the main processor and stored in external memory. If no place is available in the sys-
tem level ring buffer, the data is held in the FIFO.
When the GRTC keeps receiving data, the FIFO will fill up and when it reaches 100% of data, and the
hold and shift registers are full, a receiver overrun interrupt will be generated (IRQ_RX_OVER-
RUN). All new incoming data is rejected until space is available in the peripheral FIFO.
When the receiving data stream is stopped (e.g. when a complete data block is received), and some
bytes are still in the peripheral FIFO, then these bytes will be transmitted to the system level ring buf-
fer automatically. Received bytes in the shift and hold register are always directly transferred to the
peripheral FIFO.
The FIFO is automatically emptied when a CLTU is either ready or has been abandoned. The reason
for the latter can be codeblock error, time out etc. as described in CLTU decoding state diagram.
The operational state machine is shown in figure 79.
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