COBHAM GR712RC - 3.10 Test mode clocking

GR712RC-UM, Jun 2017, Version 2.9 35 www.cobham.com/gaisler
GR712RC
The LEON3FT processor cores will automatically be clock gated when the processor enter power-
down or halt state. The floating-point units (GRFPU) will be clock gated when the corresponding pro-
cessor have disabled FPU operations by setting the %psr.ef bit to zero, or when the processor have
entered power-down/halt mode. For more information see the chapter about the clock gating unit.
3.10 Test mode clocking
When in test mode (TESTEN signal = 1) all clocks in the design are connected to the INCLK test
clock.