COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 36 www.cobham.com/gaisler
GR712RC
4 LEON3FT - High-performance SPARC V8 32-bit Processor
4.1 Overview
The GR712RC implements two LEON3FT processor cores in SMP configuration. LEON3FT is a 32-
bit processor core conforming to the IEEE-1754 (SPARC V8) architecture. It is designed for embed-
ded applications, combining high performance with low complexity and low power consumption.
The LEON3FT core has the following main features: 7-stage pipeline with Harvard architecture, sep-
arate instruction and data caches, hardware multiplier and divider, on-chip debug support and multi-
processor extensions.
4.1.1 Integer unit
The LEON3 integer unit implements the full SPARC V8 standard, including hardware multiply and
divide instructions. The number of register windows is 8. The pipeline consists of 7 stages with a sep-
arate instruction and data cache interface (Harvard architecture).
4.1.2 Cache sub-system
Each processor is configured with a 16 KiB instruction cache and a 16 KiB data cache. The instruc-
tion cache uses streaming during line-refill to minimize refill latency. The data cache uses write-
through policy and implements a double-word write-buffer. The data cache can also perform bus-
snooping on the AHB bus.
4.1.3 Floating-point unit
Each LEON3 processor is connected to a unique GRFPU floating-point unit. The GRFPU implements
the IEEE-754 floating-point format and supports both single and double-precision operands.
4.1.4 Memory management unit
A SPARC V8 Reference Memory Management Unit (SRMMU) is provided per processor. The
SRMMU implements the full SPARC V8 MMU specification, and provides mapping between multi-
ple 32-bit virtual address spaces and 32-bit physical memory. A three-level hardware table-walk is
implemented, and the MMU is configured with 32 fully associative TLB entries.
Integer pipeline
I-Cache D-Cache
3-Port Register File
AMBA AHB Master (32-bit)
AHB I/F
7-Stage
Interrupt controller
Co-Processor
HW MUL/DIV
IEEE-754 FPU
Trace Buffer
Debug port
Interrupt port
Debug support unit
Figure 2. LEON3 processor core block diagram
SRMMU
DTLB
ITLB

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English