COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 100 www.cobham.com/gaisler
GR712RC
15.5 FIFO debug mode
FIFO debug mode is entered by setting the debug mode bit in the control register. In this mode it is
possible to read the transmitter FIFO and write the receiver FIFO through the FIFO debug register.
The transmitter output is held inactive when in debug mode. A write to the receiver FIFO generates an
interrupt if receiver interrupts are enabled.
15.6 Interrupt generation
For FIFOs, two different kinds of interrupts are available: normal interrupts and FIFO interrupts. For
the transmitter, normal interrupts are generated when transmitter interrupts are enabled (TI), the trans-
mitter is enabled and the transmitter FIFO goes from containing data to being empty. FIFO interrupts
are generated when the FIFO interrupts are enabled (TF), transmissions are enabled (TE) and the
UART is less than half-full (that is, whenever the TH status bit is set). This is a level interrupt and the
interrupt signal is continuously driven high as long as the condition prevails. The receiver interrupts
work in the same way. FIFO interrupts are generated when receiver FIFO interrupts are enabled, the
receiver is enabled and the FIFO is half-full. The interrupt signal is continuously driven high as long
as the receiver FIFO is half-full (at least half of the entries contain data frames).
15.7 Registers
The core is controlled through registers mapped into APB address space.
Table 76. UART register start address
APB address UART device Interrupt
0x80000100 UART 0 2
0x80100100 UART 1 17
0x80100200 UART 2 18
0x80100300 UART 3 19
0x80100400 UART 4 20
0x80100500 UART 5 21
Table 77. UART registers
APB address offset Register
0x0 UART Data register
0x4 UART Status register
0x8 UART Control register
0xC UART Scaler register
0x10 UART FIFO debug register

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English