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tion is resident in the cache but not executed for a long period of time. In such cases, executing a
cache flush instruction periodically (e.g. once per minute) is sufficient to refresh the cache contents.
4.8.6 Initialisation
After power-on, the check bits in the IU register file are not initialized. This means that access to an
uninitialized (un-written) register could cause a register access trap (tt = 0x20). Such behaviour is
considered as a software error, as the software should not read a register before it has been written. It
is recommended that the boot code for the processor writes all registers in the IU register files before
launching the main application.
The check bits in the cache memories do not need to be initialized as this is done automatically during
cache line filling. However, a cache flush must be executed before the caches are enabled.
4.9 Signal definitions
When the processor enters error mode, the ERRORN output is driven active low, else it is in tri-state
and therefore requires an additional external pull-up.
The signals are described in table 23.
Table 23. Signal definitions
Signal name Type Function Active
ERRORN Tri-state output Processor error mode indicator Low
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