GR712RC-UM, Jun 2017, Version 2.9 34 www.cobham.com/gaisler
GR712RC
3.8 SDRAM clock
The SDRAM clock (SDCLK) output is driven from the internal system clock. A programmable delay
line allows tuning the SDCLK phase relative to the internal clock. The output is tuned to be in phase
with the internal clock tree when the delay line is set to zero. If the system clock is generated by the 2x
MFDLL, SDCLK is not active when the reset input (RESETN) is asserted. When the system clock is
generated directly from INCLK (i.e. when DLLBPN = 0), then SDCLK is driven directly from
INCLK passing through the Delay line.
3.9 Clock gating unit
The GR712RC device has a clock gating unit through which individual cores can have their AHB
clocks enabled/disabled and resets driven. The cores connected to the clock gating unit are listed in
the table below:
Table 13. Devices with gatable clock
Device
Ethernet
SpaceWire 0
SpaceWire 1
SpaceWire 2
SpaceWire 3
SpaceWire 4
SpaceWire 5
CAN 0 - 1
Proprietary
CCSDS Telemetry
CCSDS Telecommand
MIL-STD-1553
LEON3FT (0)
LEON3FT (1)
GRFPU(0)
GRFPU(1)
System clock (CLK)
Delay line SDCLK
SDDELAY
Ctrl, Write data
Read data
Memory
Controller
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