COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 195 www.cobham.com/gaisler
GR712RC
26.9 Registers
The core is programmed through registers mapped into AHB I/O address space.
Table 206.GRTC registers
AHB address Register
0xFFF10000 Global Reset Register (GRR)
0xFFF10004 Global Control Register (GCR)
0xFFF10008 Physical Interface Mask Register (PMR)
0xFFF1000C Spacecraft Identifier Register (SIR)
0xFFF10010 Frame Acceptance Report Register (FAR)
0xFFF10014 CLCW Register 1 (CLCWR1)
0xFFF10018 CLCW Register 2 (CLCWR2)
0xFFF1001C Physical Interface Register (PHIR)
0xFFF10020 Control Register (COR)
0xFFF10024 Status Register (STR)
0xFFF10028 Address Space Register (ASR)
0xFFF1002C Receive Read Pointer Register (RRP)
0xFFF10030 Receive Write Pointer Register (RWP)
0xFFF10060 Pending Interrupt Masked Status Register (PIMSR)
0xFFF10064 Pending Interrupt Masked Register (PIMR)
0xFFF10068 Pending Interrupt Status Register (PISR)
0xFFF1006C Pending Interrupt Register (PIR)
0xFFF10070 Interrupt Mask Register (IMR)
0xFFF10074 Pending Interrupt Clear Register (PICR)
Table 207. Global Reset Register (GRR)
31 24 23 10
SEB RESERVED SRST
31: 24 SEB (Security Byte):
Write: ‘0x55’= the write will have effect (the register will be updated). 
Any other value= the write will have no effect on the register.
Read: All zero.
23: 1 RESERVED
Write: Don’t care.
Read: All zero.
0 System reset (SRST):
[1]
Write: ‘1’= initiate reset,‘0’= do nothing
Read: ‘1’= unsuccessful reset, ‘0’= successful reset
Power-up default: 0x00000000
Table 208. Global Control Register (GCR)
31 24 23 13 12 11 10 9 0
SEB RESERVED PSS NRZM PSR RESERVED
31: 24 SEB (Security Byte):
Write: ‘0x55’= the write will have effect (the register will be updated). 
Any other value= the write will have no effect on the register.
Read: All zero.

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English