GR712RC-UM, Jun 2017, Version 2.9 58 www.cobham.com/gaisler
GR712RC
5.5 8-bit PROM and SRAM access
To support applications with low memory and performance requirements efficiently, the SRAM and
PROM areas can be individually configured for 8-bit operation by programming the ROM and RAM
width fields in the memory configuration registers. Since reads to memory are always done on 32-bit
word basis, read access to 8-bit memory will be transformed in a burst of four read cycles. During
writes, only the necessary bytes will be written. Figure 26 shows an interface example with 8-bit
PROM and 8-bit SRAM.
The supported combinations of width, EDAC and RMW for the PROM and SRAM areas are given in
table 24.
The RMW bit in MCFG2 must not be set if RAM EDAC is dissembled when RAM width is set to 8-
bit.
Table 24. Supported SRAM and PROM width, EDAC and RMW combinations
Bus width EDAC RMW bit (SRAM only)
8 None 0
8BCH1
32 None 1
32+7 BCH 1
Figure 25. Sram read-modify-write cycle (0-waitstates)
wdata
address
ramsn
data
ramwen
cb
lead-out
clk
A1
D1
CB1
nD1
oen,
ramoen
nCB1
rdata1 rdata2 modify
read
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