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COBHAM GR712RC User Manual

COBHAM GR712RC
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GR712RC-UM, Jun 2017, Version 2.9 88 www.cobham.com/gaisler
GR712RC
11.3 Registers
The core is programmed through registers mapped at address 0x80000300.
Table 48. GPTIMER unit registers
APB address Register Reset value
0x80000300 Scaler value 0xFFFF
0x80000304 Scaler reload value 0xFFFF
0x80000308 Configuration register 0x0044
0x80000310 Timer 1 counter value register -
0x80000314 Timer 1 reload value register -
0x80000318 Timer 1 control register IE=0, EN=0
0x80000320 Timer 2 counter value register -
0x80000324 Timer 2 reload value register -
0x80000328 Timer 2 control register IE=0, EN=0
0x80000330 Timer 3 counter value register -
0x80000334 Timer 3 reload value register -
0x80000338 Timer 3control register IE=0, EN=0
0x80000340 Timer 4 counter value register 0xFFFF
0x80000344 Timer 4 reload value register 0xFFFF
0x80000348 Timer 4 control register 0x0009
Table 49. Scaler value
31 16 15 0
“000..0 SCALER VALUE
15: 0 Scaler value
Any unused most significant bits are reserved. Always reads as ‘000...0’.
Table 50. Scaler reload value
31 16 15 0
“000..0” SCALER RELOAD VALUE
15: 0 Scaler reload value
Any unused most significant bits are reserved. Always read as ‘000...0’.
Table 51. GPTIMER Configuration register
31 10 9 8 7 3 2 0
“000..0” DF SI IRQ TIMERS
31: 10 Reserved. Write only with zeroes.
9 Disable timer freeze (DF). If set the timer unit can not be freezed, otherwise timers will halt when
the processor enters debug mode.
8 Separate interrupts (SI). Reads ‘1’ to indicate the timer unit generates separate interrupts for each
timer.
7: 3 Interrupt ID of first timer. Set to 8. Read-only.
2: 0 Number of implemented timers. Set to 4. Read-only.
Table 52. Timer counter value register
31 0
TIMER COUNTER VALUE

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COBHAM GR712RC Specifications

General IconGeneral
BrandCOBHAM
ModelGR712RC
CategoryComputer Hardware
LanguageEnglish

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