COBHAM GR712RC - Default Chapter; Table of Contents

GR712RC-UM, Jun 2017, Version 2.9 2 www.cobham.com/gaisler
GR712RC
Table of contents
1 Introduction........................................................................................................... 7
1.1 Scope...................................................................................................................... 7
1.2 GR712RC Architecture .......................................................................................... 7
1.3 Memory map .......................................................................................................... 8
1.4 Interrupts ................................................................................................................ 9
1.5 GRLIB IP cores...................................................................................................... 9
1.6 References............................................................................................................ 10
1.7 Errata.....................................................................................................................11
1.8 Document revision history ................................................................................... 18
2 Signals and I/O Switch Matrix........................................................................... 22
3 Clocking ............................................................................................................... 32
3.1 System clock ........................................................................................................ 32
3.2 SpaceWire clock................................................................................................... 32
3.3 MIL-STD-1553 .................................................................................................... 33
3.4 Telemetry ............................................................................................................. 33
3.5 Telecommand ....................................................................................................... 33
3.6 Obsolete ............................................................................................................... 33
3.7 SLINK.................................................................................................................. 33
3.8 SDRAM clock...................................................................................................... 34
3.9 Clock gating unit.................................................................................................. 34
3.10 Test mode clocking .............................................................................................. 35
4 LEON3FT - High-performance SPARC V8 32-bit Processor......................... 36
4.1 Overview.............................................................................................................. 36
4.2 LEON3 integer unit.............................................................................................. 37
4.3 Instruction cache .................................................................................................. 44
4.4 Data cache ............................................................................................................ 45
4.5 Additional cache functionality ............................................................................. 46
4.6 Memory management unit ................................................................................... 48
4.7 Floating-point unit................................................................................................ 50
4.8 Error detection and correction.............................................................................. 50
4.9 Signal definitions ................................................................................................. 52
5 Fault Tolerant Memory Controller.................................................................... 53
5.1 Overview.............................................................................................................. 53
5.2 PROM access ....................................................................................................... 54
5.3 Memory mapped IO ............................................................................................. 56
5.4 SRAM access ....................................................................................................... 57
5.5 8-bit PROM and SRAM access ........................................................................... 58
5.6 8- bit I/O access.................................................................................................... 59
5.7 Burst cycles .......................................................................................................... 59
5.8 SDRAM access .................................................................................................... 59
5.9 Refresh ................................................................................................................. 60
5.10 Memory EDAC .................................................................................................... 62
5.11 Bus Ready signalling ........................................................................................... 64