COBHAM GR712RC - Page 3

GR712RC-UM, Jun 2017, Version 2.9 3 www.cobham.com/gaisler
GR712RC
5.12 External bus errors ............................................................................................... 65
5.13 Read strobe........................................................................................................... 66
5.14 Registers............................................................................................................... 66
5.15 Signal definitions ................................................................................................. 69
6 On-chip Memory with EDAC Protection ......................................................... 70
6.1 Overview.............................................................................................................. 70
6.2 Operation.............................................................................................................. 70
6.3 Registers............................................................................................................... 71
7 AHB Status Registers ......................................................................................... 72
7.1 Overview.............................................................................................................. 72
7.2 Operation.............................................................................................................. 72
7.3 Registers............................................................................................................... 72
8 Multiprocessor Interrupt Controller................................................................. 73
8.1 Overview.............................................................................................................. 73
8.2 Operation.............................................................................................................. 73
8.3 Registers............................................................................................................... 75
9 Hardware Debug Support Unit ......................................................................... 78
9.1 Overview.............................................................................................................. 78
9.2 Operation.............................................................................................................. 78
9.3 AHB Trace Buffer................................................................................................ 79
9.4 Instruction trace buffer......................................................................................... 80
9.5 DSU memory map ............................................................................................... 81
9.6 DSU registers ....................................................................................................... 82
10 JTAG Debug Interface........................................................................................ 85
10.1 Overview.............................................................................................................. 85
10.2 Operation.............................................................................................................. 85
10.3 Registers............................................................................................................... 86
10.4 Signal definitions ................................................................................................. 86
11 General Purpose Timer Unit.............................................................................. 87
11.1 Overview.............................................................................................................. 87
11.2 Operation.............................................................................................................. 87
11.3 Registers............................................................................................................... 88
11.4 Signal definitions ................................................................................................. 89
12 General Purpose Timer Unit with Time Latch Capability.............................. 90
12.1 Overview.............................................................................................................. 90
12.2 Operation.............................................................................................................. 90
12.3 Registers............................................................................................................... 91
13 General Purpose Register................................................................................... 93
13.1 Operation.............................................................................................................. 93
13.2 Registers............................................................................................................... 93
14 General Purpose I/O Port .................................................................................. 94
14.1 Overview.............................................................................................................. 94
14.2 Operation.............................................................................................................. 94
14.3 Registers............................................................................................................... 96