GR712RC-UM, Jun 2017, Version 2.9 11 www.cobham.com/gaisler
GR712RC
1.7 Errata
1.7.1 FTAHBRAM: On-chip Memory not cacheable
The 192 KiB on-chip memory at address 0xA00000000 is not cacheable in the L1 caches of the pro-
cessors. This means that executing from the on-chip memory will be slow, approximately 0.25 MIPS/
MHz. The on-chip memory should preferably be used for data storage for on-chip IP cores, such as
the Mil-Std-1553B controller, Ethernet controller and SpaceWire links.
See sections
4.2.16 and 6.1 for details.
1.7.2 CAN OC: interrupt can be cleared before read
The Transmit Interrupt can be cleared before read, if a read access is made to the Interrupt Register in
the same clock cycle as the interrupt is set by the transmitter logic.
Instead of looking at the Transmit Interrupt flag, the Transmit Buffer Status flag in the Status Register
can bee looked at when something has been scheduled for transmission.
See section 18.4.5.
1.7.3 GRSPW2: interrupt can be lost
If an AMBA AHB error occurs in the same clock cycle as a SpaceWire link error or Time-Code Tick-
Out interrupt is generated and the AMBA AHB error interrupts are disabled then the corresponding
interrupt will be lost (i.e. SpaceWire link error or Time-Code Tick-Out interrupt)
The workaround is to also enable the AMBA AHB error interrupt when any of the link error or Time-
Code Tick-Out interrupts are enabled. An AMBA AHB error interrupt will cause the corresponding
DMA channel to stop, and therefore interrupt handling will be required anyway.
See section 16.9.
1.7.4 GRSPW2: CRC calculation partially incorrect
RMAP CRC calculation for the DMA receiver does not work correctly under all conditions. The
detected header length is not used correctly in cases when two characters are received on consecutive
cycles and one of them is the header CRC. This results in an incorrect header CRC indication in the
receiver descriptor (i.e. Header CRC (HC) field). The calculation is continued however (as described
in the manual) and the data CRC indication (i.e. Data CRC (DC) field) is still correct and covers the
whole packet and can thus be used to determine that there are no errors in the complete packet.
See section 16.4.5.
1.7.5 SPICTRL: transfers in progress bit not cleared
The Transfer in Progress bit (TIP the core's Event Register is not cleared automatically by the core if
an overrun occurs. The core needs to be disabled in order to clear the bit. The problem does not affect
most software drivers.
Workaround 1: Read receive queue so that no overrun occurs.
Workaround 2: Disable and re-enable core if overrun occurs.
Workaround 3: Do not use Transfer in Progress (TIP) interrupts.
See section 23.3.
1.7.6 SPICTRL: back-to-back transfers
Back-to-back transfers where a word is written to the core's transmit queue at the very end of the
transfer of a previous word may cause the core to essentially change the clock phase (CPHA) of the
SPI communication. This leads to transmission and reception of wrong data.
The SPI controller regards a transfer as completed when the last bit has been sampled. With clock
phase 1 there is a window between sampling of the last bit and when the SCK clock line returns to its
idle state. If a new transfer is started (a word is written to the core's transmit queue) in this window,
then the bug will be triggered.
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