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16.4.2 Basic functionality of a channel
Reception is based on descriptors located in a consecutive area in memory that hold pointers to buf-
fers where packets should be stored. When a packet arrives at the GRSPW the channel which should
receive it is first determined as described in the previous section. A descriptor is then read from the
channels’ descriptor area and the packet is stored to the memory area pointed to by the descriptor.
Lastly, status is stored to the same descriptor and increments the descriptor pointer to the next one.
The following sections will describe DMA channel reception in more detail.
16.4.3 Setting up the GRSPW for reception
A few registers need to be initialized before reception to a channel can take place. First the link inter-
face need to be put in the run state before any data can be sent. The DMA channel has a maximum
length register which sets the maximum packet size in bytes that can be received to this channel.
Larger packets are truncated and the excessive part is spilled. If this happens an indication will be
given in the status field of the descriptor. The minimum value for the receiver maximum length field
is 4 and the value can only be incremented in steps of four bytes up to the maximum value 33554428.
If the maximum length is set to zero the receiver will not function correctly.
Either the default address register or the channel specific address register (the accompanying mask
register must also be set) needs to be set to hold the address used by the channel. A control bit in the
DMA channel control register determines whether the channel should use default address and mask
registers for address comparison or the channel’s own registers. Using the default register the same
address range is accepted as for RMAP commands while the separate provides the channel it own
range. If all channels use the default registers they will accept the same address range and the enabled
channel with the lowest number will receive the packet.
Finally, the descriptor table and control register must be initialized. This will be described in the two
following sections.
16.4.4 Setting up the descriptor table address
The GRSPW reads descriptors from an area in memory pointed to by the receiver descriptor table
address register. The register consists of a base address and a descriptor selector. The base address
points to the beginning of the area and must start on a 1024 bytes aligned address. It is also limited to
be 1024 bytes in size which means the maximum number of descriptors is 128 since the descriptor
size is 8 bytes.
The descriptor selector points to individual descriptors and is increased by 1 when a descriptor has
been used. When the selector reaches the upper limit of the area it wraps to the beginning automati-
cally. It can also be set to wrap at a specific descriptor before the upper limit by setting the wrap bit in
the descriptor. The idea is that the selector should be initialized to 0 (start of the descriptor area) but it
can also be written with another 8 bytes aligned value to start somewhere in the middle of the area. It
will still wrap to the beginning of the area.
If one wants to use a new descriptor table the receiver enable bit has to be cleared first. When the
rxactive bit for the channel is cleared it is safe to update the descriptor table register. When this is fin-
ished and descriptors are enabled the receiver enable bit can be set again.
16.4.5 Enabling descriptors
As mentioned earlier one or more descriptors must be enabled before reception can take place. Each
descriptor is 8 byte in size and the layout can be found in the tables below. The descriptors should be
written to the memory area pointed to by the receiver descriptor table address register. When new
descriptors are added they must always be placed after the previous one written to the area. Otherwise
they will not be noticed.
A descriptor is enabled by setting the address pointer to point at a location where data can be stored
and then setting the enable bit. The WR bit can be set to cause the selector to be set to zero when
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