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GR712RC
reception has finished to this descriptor. IE should be set if an interrupt is wanted when the reception
has finished. The DMA control register interrupt enable bit must also be set for an interrupt to be gen-
erated.
The descriptor packet address should be word aligned. All accesses on the bus are word accesses so
complete words will always be overwritten regardless of whether all 32-bit contain received data.
Also if the packet does not end on a word boundary the complete word containing the last data byte
will be overwritten.
16.4.6 Setting up the DMA control register
The final step to receive packets is to set the control register in the following steps: The receiver must
be enabled by setting the rxen bit in the DMA control register. This can be done anytime and before
this bit is set nothing will happen. The rxdescav bit in the DMA control register is then set to indicate
that there are new active descriptors. This must always be done after the descriptors have been
enabled or the GRSPW might not notice the new descriptors. More descriptors can be activated when
reception has already started by enabling the descriptors and writing the rxdescav bit. When these bits
are set reception will start immediately when data is arriving.
16.4.7 The effect to the control bits during reception
When the receiver is disabled all packets going to the DMA-channel are discarded if the packet’s
address does not fall into the range of another DMA channel. If the receiver is enabled and the address
falls into the accepted address range, the next state is entered where the rxdescav bit is checked. This
bit indicates whether there are active descriptors or not and should be set by the external application
using the DMA channel each time descriptors are enabled as mentioned above. If the rxdescav bit is
‘0’ and the nospill bit is ‘0’ the packets will be discarded. If nospill is one the GRSPW waits until
rxdescav is set and the characters are kept in the N-Char fifo during this time. If the fifo becomes full
further N-char transmissions are inhibited by stopping the transmission of FCTs.
Table 84. GRSPW receive descriptor word 0 (address offset 0x0)
31 30 29 28 27 26 25 24 0
TR DC HC EP IE WR EN PACKETLENGTH
31 Truncated (TR) - Packet was truncated due to maximum length violation.
30 Data CRC (DC) - 1 if a CRC error was detected for the data and 0 otherwise.
29 Header CRC (HC) - 1 if a CRC error was detected for the header and 0 otherwise.
28 EEP termination (EP) - This packet ended with an Error End of Packet character.
27 Interrupt enable (IE) - If set, an interrupt will be generated when a packet has been received if the
receive interrupt enable bit in the DMA channel control register is set.
26 Wrap (WR) - If set, the next descriptor used by the GRSPW will be the first one in the descriptor
table (at the base address). Otherwise the descriptor pointer will be increased with 0x8 to use the
descriptor at the next higher memory location. The descriptor table is limited to 1 KiB in size and the
pointer will be automatically wrap back to the base address when it reaches the 1 KiB boundary.
25 Enable (EN) - Set to one to activate this descriptor. This means that the descriptor contains valid con-
trol values and the memory area pointed to by the packet address field can be used to store a packet.
24: 0 Packet length (PACKETLENGTH) - The number of bytes received to this buffer. Only valid after
EN has been set to 0 by the GRSPW.
Table 85. GRSPW receive descriptor word 1 (address offset 0x4)
31 0
PACKETADDRESS
31: 0 Packet address (PACKETADDRESS) - The address pointing at the buffer which will be used to store
the received packet.
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