COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 111 www.cobham.com/gaisler
GR712RC
When rxdescav is set the next descriptor is read and if enabled the packet is received to the buffer. If
the read descriptor is not enabled, rxdescav is set to ‘0’ and the packet is spilled depending on the
value of nospill.
The receiver can be disabled at any time and will stop packets from being received to this channel. If
a packet is currently received when the receiver is disabled the reception will still be finished. The
rxdescav bit can also be cleared at any time. It will not affect any ongoing receptions but no more
descriptors will be read until it is set again. Rxdescav is also cleared by the GRSPW when it reads a
disabled descriptor.
16.4.8 Status bits
When the reception of a packet is finished the enable (EN) bit in the current descriptor is cleared to
zero. Notet that alos the interrupt enable (IE) and Wrap (WR) bits are cleared to zero. When enable is
zero, the status bits are also valid and the number of received bytes is indicated in the length field. The
DMA control register contains a status bit which is set each time a packet has been received. The
GRSPW can also be made to generate an interrupt for this event as mentioned in section.
RMAP CRC is always checked for all packets when CRC logic is included in the implementation . All
bytes in the packet except the EOP/EEP is included in the CRC calculation. The packet is always
assumed to be a RMAP packet and the length of the header is determined by checking byte 3 which
should be the command field. The calculated CRC value is then checked when the header has been
received (according to the calculated number of bytes) and if it is non-zero the HC bit is set indicating
a header CRC error.
The CRC value is not set to zero after the header has been received, instead the calculation continues
in the same way until the complete packet has been received. Then if the CRC value is non-zero the
DC bit is set indicating a data CRC error. This means that the GRSPWcan indicate a data CRC error
even if the data field was correct when the header CRC was incorrect. However, the data should not
be used when the header is corrupt and therefore the DC bit is unimportant in this case. When the
header is not corrupted the CRC value will always be zero when the calculation continues with the
data field and the behaviour will be as if the CRC calculation was restarted
If the received packet is not of RMAP type the header CRC error indication bit cannot be used. It is
still possible to use the DC bit if the complete packet is covered by a CRC calculated using the RMAP
CRC definition. This is because the GRSPW does not restart the calculation after the header has been
received but instead calculates a complete CRC over the packet. Thus any packet format with one
CRC at the end of the packet calculated according to RMAP standard can be checked using the DC
bit.
If the packet is neither of RMAP type nor of the type above with RMAP CRC at the end, then both the
HC and DC bits should be ignored.
16.4.9 Error handling
If a packet reception needs to be aborted because of congestion on the network, the suggested solution
is to set link disable to ‘1’. Unfortunately, this will also cause the packet currently being transmitted to
be truncated but this is the only safe solution since packet reception is a passive operation depending
on the transmitter at the other end. A channel reset bit could be provided but is not a satisfactory solu-
tion since the untransmitted characters would still be in the transmitter node. The next character
(somewhere in the middle of the packet) would be interpreted as the node address which would prob-
ably cause the packet to be discarded but not with 100% certainty. Usually this action is performed
when a reception has stuck because of the transmitter not providing more data. The channel reset
would not resolve this congestion.
If an AHB error occurs during reception the current packet is spilled up to and including the next
EEP/EOP and then the currently active channel is disabled and the receiver enters the idle state. A bit
in the channels control/status register is set to indicate this condition.

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English