COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 129 www.cobham.com/gaisler
GR712RC
17.3 Tx DMA interface
The transmitter DMA interface is used for transmitting data on an Ethernet network. The transmission
is done using descriptors located in memory.
17.3.1 Setting up a descriptor.
A single descriptor is shown in table 106 and 107. The number of bytes to be sent should be set in the
length field and the address field should point to the data. The address must be word-aligned. If the
interrupt enable (IE) bit is set, an interrupt will be generated when the packet has been sent (this
requires that the transmitter interrupt bit in the control register is also set). The interrupt will be gener-
ated regardless of whether the packet was transmitted successfully or not. The Wrap (WR) bit is also a
control bit that should be set before transmission and it will be explained later in this section.
To enable a descriptor the enable (EN) bit should be set and after this is done, the descriptor should
not be touched until the enable bit has been cleared by the GRETH.
17.3.2 Starting transmissions
Enabling a descriptor is not enough to start a transmission. A pointer to the memory area holding the
descriptors must first be set in the GRETH. This is done in the transmitter descriptor pointer register.
The address must be aligned to a 1 kB boundary. Bits 31 to 10 hold the base address of descriptor area
while bits 9 to 3 form a pointer to an individual descriptor.The first descriptor should be located at the
base address and when it has been used by the GRETH the pointer field is incremented by 8 to point at
the next descriptor. The pointer will automatically wrap back to zero when the next 1 kB boundary has
been reached (the descriptor at address offset 0x3F8 has been used). The WR bit in the descriptors can
be set to make the pointer wrap back to zero before the 1 kB boundary.
Table 106. GRETH transmit descriptor word 0 (address offset 0x0)
31 16 15 14 13 12 11 10 0
RESERVED AL UE IE WR EN LENGTH
31: 16 RESERVED
15 Attempt Limit Error (AL) - The packet was not transmitted because the maximum number of
attempts was reached.
14 Underrun Error (UE) - The packet was incorrectly transmitted due to a FIFO underrun error.
13 Interrupt Enable (IE) - Enable Interrupts. An interrupt will be generated when the packet from this
descriptor has been sent provided that the transmitter interrupt enable bit in the control register is set.
The interrupt is generated regardless if the packet was transmitted successfully or if it terminated
with an error.
12 Wrap (WR) - Set to one to make the descriptor pointer wrap to zero after this descriptor has been
used. If this bit is not set the pointer will increment by 8. The pointer automatically wraps to zero
when the 1 kB boundary of the descriptor table is reached.
11 Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor
fields.
10: 0 LENGTH - The number of bytes to be transmitted.
Table 107. GRETH transmit descriptor word 1 (address offset 0x4)
31 210
ADDRESS RES
31: 2 Address (ADDRESS) - Pointer to the buffer area from where the packet data will be loaded.
1: 0 RESERVED

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English