GR712RC-UM, Jun 2017, Version 2.9 128 www.cobham.com/gaisler
GR712RC
17 Ethernet Media Access Controller (MAC)
17.1 Overview
The Ethernet Media Access Controller (GRETH) provides an interface between an AMBA-AHB bus
and an Ethernet network. It supports 10/100 Mbit speed in both full- and half-duplex. The AMBA
interface consists of an APB interface for configuration and control and an AHB master interface for
transmit and receive data. There is one DMA engine for the transmitter and one for the receiver. Both
share the same AHB master interface. The ethernet interface supports the RMII interfaces which
should be connected to an external PHY. The GRETH also provides access to the RMII Management
interface which is used to configure the PHY.
17.2 Operation
17.2.1 Protocol support
The GRETH is implemented according to IEEE standard 802.3-2002. There is no support for the
optional control sublayer and no multicast addresses can be assigned to the MAC. This means that
packets with type 0x8808 (the only currently defined ctrl packets) are discarded.
17.2.2 Clocking
GRETH has two clock domains: The AHB clock and the Ethernet PHY clock. The ethernet transmit-
ter and receiver clock is generated by the external ethernet PHY, and is an input to the core through
the REFCLK signal. The two clock domains are unrelated to each other and all signals crossing the
clock regions are fully synchronized inside the core.
Both full-duplex and half-duplex operating modes are supported and both can be run in either 10 or
100 Mbit. The minimum AHB clock for 10 Mbit operation is 2.5 MHz, while 18 MHz is needed for
100 Mbit. Using a lower AHB clock than specified will lead to excessive packet loss.
AHB
APB
Ethernet MAC
Registers
MDIO
RMMDIO
RMMDC
AHB Master
Interface
Transmitter
Receiver
Transmitter
Receiver
DMA Engine
DMA Engine
FIFO
FIFO
RMTXEN
RMTXD(1:0)
RMRFCLK
RMCRSDV
RMRXD(1:0)
Figure 64. Block diagram of the internal structure of the GRETH with RMII
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