GR712RC-UM, Jun 2017, Version 2.9 180 www.cobham.com/gaisler
GR712RC
25 ASCS Controller
25.1 Overview
The ASCS core provides a serial link that performs data reads (telemetry) and data writes (telecom-
mand). The core supports 2 slaves, data word lengths of 16 bits, and different frequencies for the syn-
chronization link (in the 1 - 100 Hz range, for all supported system frequencies).
25.2 Operation
25.2.1 Serial link
The task of the serial link is to perform data writes (telecommand, TC) and data reads (telemetry,
TM). The interface of the serial link consists of five signals: hs, dcs, mcs, mas, das. The hs signal is
the serial clock (500 kHz) signal used to control the TC or TM; dcs is the data output from the host to
the slaves; mcs indicates that a TC is about to start or finish; mas indicates that a TM is about to start
or finish; das is the data input from the slaves to the host. The core supports both a configuration
where each slave has its own data input and a configuration where only one data input is used, and
where the slaves are assumed to tri-state their output. For a more detailed description of how a single
TC/TM is performed and the timing requirements that apply please refer to the ASCS specification.
The activity on the serial link is controlled through the core’s command and control register, status
register, TC data register, and TM data register (see 25.3). The following also needs to be taken into
consideration:
• For transactions to be timed correctly the us1 field of the command register must be setup.
• A TC and TM will never be performed at the same time.
• The serial link must be running for a TC or TM to be carried out. If the serial link is stopped and
software tells the core to start a transfer, the transfer will be delayed until the serial link is started.
• The GRASCS has no FIFO where it buffers transfer requests or data. However since separate
registers are used for TC and TM the core can handle that software starts one TC and one TM at
the same time. In such a case the TC will always be performed before the TM.
• Once a transfer has been started by software the only way to abort it is to reset the core.
• There might be a delay between the time software starts a transfer and the time the core performs
it. This delay could be because the core is still waiting for the minimum delay time between
transfers to pass. A TM can also be delay up to 150 microseconds if a synchronization pulse is
being generated.
25.2.2 Synchronization link
The task of the synchronization link is to issue synchronization pulses to the slaves. The interface of
the synchronization link consists of one signal called etr. When the link is running the core generates
pulses on the etr signal. The frequency of the etr pulses can be configured through the core’s ETR
scale register. The synchronization link is controlled through the core’s command and control register
and status register. The following also needs to be taken into consideration:
• For synchronization pulses to be generated correctly the ETR scale register must be set properly.
• When software starts the synchronization interface the core might delay the actual start of the
interface. The reason for this could be that a TM is in progress. It could also be because the inter-
nal ETR timer, which is always running, is in the middle of a pulse. The core then delays the start
to be sure not to generate an external pulse that is too short.
• The first pulse on the etr signal might be delayed with up to one period from the time that the
core starts the synchronization interface, depending on the source used to generate the pulse.
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