COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 93 www.cobham.com/gaisler
GR712RC
13 General Purpose Register
13.1 Operation
The GRGPREG provides a programmable register that controls clock generation and multiplexing.
13.2 Registers
The core is programmed through registers mapped into APB address space.
This register resets to 0.
Table 65. General Purpose Register
APB address offset Register
0x80000600 General purpose register
Table 66. I/O port data register
2619181716151413 65 4 3210
SDCLK Del. DIVO 1553DIVL 1553DIVH RESERVED 1553 clock SpW rst TM clk SpW clk SpW src
31 - 27 Reserved
26 - 19 Programable SDCLK delay, number of stages in the programmable delay line (0 - 255)
18 MIL-STD-1553B clock divider output: 1- system clock, 0 = divided clock
17 - 16 MIL-STD-1553B clock divider low count, clock is low DIVL+1 system clock cycles
15 - 14 MIL-STD-1553B clock divider high count, clock is high DIVH+1 system clock cycles
13 - 6 Reserved, always write all zeros to this field
5 MIL-STD-1553B clock select: 0 - generated clock, 1 - 1553CK input
4 SpaceWire DLL reset (active low)
3 TM clock select: 0 - TMCLKI, 1 - System clock
2 - 1: SpaceWire clock select: 0 - 1X, 1 - System clock, 2 - 2X, 3 - 4X
0 SpaceWire clock source: 0 - SPWCLK, 1 - INCLK

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English