COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 37 www.cobham.com/gaisler
GR712RC
4.1.5 On-chip debug support
The LEON3 pipeline includes functionality to allow non-intrusive debugging on target hardware.
Through the JTAG debug support interface, full access to all processor registers and caches is pro-
vided. The debug interfaces also allows single stepping, instruction tracing and hardware breakpoint/
watchpoint control. An internal trace buffer can monitor and store executed instructions, which can
later be read out over the debug interface.
4.1.6 Interrupt interface
LEON3 supports the SPARC V8 interrupt model with a total of 15 asynchronous interrupts. The inter-
rupt interface provides functionality to both generate and acknowledge interrupts. The GR712RC
contains an interrupt controller that support 31 system interrupts, mapped on the 15 processor inter-
rupts.
4.1.7 AMBA interface
The cache system implements an AMBA AHB master to load and store data to/from the caches. The
interface is compliant with the AMBA-2.0 standard. During line refill, incremental burst are gener-
ated to optimise the data transfer.
4.1.8 Power-down mode
The LEON3 processor core implements a power-down mode, which halts the pipeline and caches
until the next interrupt using clock gating. This is an efficient way to minimize power-consumption
when the application is idle or when one of the processor cores is not used.
4.1.9 Multi-processor support
LEON3 is designed to be use in multi-processor systems and the GR712RC contains two cores. Each
processor has a unique index to allow processor enumeration. The write-through caches and snooping
mechanism guarantees memory coherency in shared-memory systems.
4.1.10 Fault-tolerance
LEON3FT contains logic to correct up to 4 bit errors per 32-bit cache word and associated tag. The
processor registers are protected by a SEC/DED BCH EDAC.
4.1.11 Performance
Using gcc-4.4.2, a dhrystone figure of 1.34 DMIPS/MHz can be achieved.
4.2 LEON3 integer unit
4.2.1 Overview
The LEON3 integer unit implements the integer part of the SPARC V8 instruction set. The implemen-
tation is focused on high performance and low complexity. The LEON3 integer unit has the following
main features:
• 7-stage instruction pipeline
• Separate instruction and data cache interface
• 8 register windows
• 16-bit Hardware multiplier and Radix-2 divider (non-restoring)
• Single-vector trapping for reduced code size

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English