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COBHAM GR712RC User Manual

COBHAM GR712RC
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GR712RC-UM, Jun 2017, Version 2.9 38 www.cobham.com/gaisler
GR712RC
Figure 3 shows a block diagram of the integer unit.
4.2.2 Instruction pipeline
The LEON integer unit uses a single instruction issue pipeline with 7 stages:
1. FE (Instruction Fetch): If the instruction cache is enabled, the instruction is fetched from the
instruction cache. Otherwise, the fetch is forwarded to the memory controller. The instruction is
valid at the end of this stage and is latched inside the IU.
2. DE (Decode): The instruction is decoded and the CALL/Branch target addresses are generated.
3. RA (Register access): Operands are read from the register file or from internal data bypasses.
4. EX (Execute): ALU operations are performed. For memory operations (e.g., LD) and for JMPL/
RETT, the address is generated.
5. ME (Memory): Data cache is accessed. Store data is written to the data cache at this time.
6. XC (Exception) Traps and interrupts are resolved. For cache reads, the data is aligned.
7. WR (Write): The result of any ALU or cache operations are written back to the register file.
Figure 3. LEON3 integer unit datapath diagram
alu/shift
mul/div
y
register file
D-cache
address/dataout
datain
32
32
operand2rs1
imm
Y
wres
result m_y
Decode
Execute
Memory
Write-back
rs2
rs1
rd
tbr, wim, psr
30
jmpl address
e pc
30
+1
d_pc
jmpa
f_pc
Add
call/branch address
tbr
ā€˜0’
e_pc
m_pc
w_pc
d_inst
e_inst
m_inst
w_inst
Fetch
I-cache
address
data
Register Access
x_y
xres
Exception
x_pcx_inst
r_pcr_inst
y, tbr, wim, psr
r_imm

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COBHAM GR712RC Specifications

General IconGeneral
BrandCOBHAM
ModelGR712RC
CategoryComputer Hardware
LanguageEnglish

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