GR712RC-UM, Jun 2017, Version 2.9 151 www.cobham.com/gaisler
GR712RC
Filter 1: ACR0.7-0 & ACR1.7-0 are compared to ID.28-13
Filter 2: ACR2.7-0 & ACR3.7-0 are compared to ID.28-13
The corresponding bits in the AMR registers selects if the results of the comparison doesn’t matter. A
set bit in the mask register means don’t care.
18.5.15 RX message counter
The RX message counter register at address 29 holds the number of
messages currently stored in the
receive fifo. The top three bits are always 0.
18.6 Common registers
There are three common registers with the same addresses and the same functionality in both Basi-
CAN and PeliCAN mode. These are the clock divider register and bus timing register 0 and 1.
18.6.1 Clock divider register
The only real function of this register in the GRLIB version of
the Opencores CAN is to choose
between PeliCAN and BasiCAN. The clkout output of the Opencore CAN core is not connected and it
is its frequency that can be controlled with this register.
18.6.2 Bus timing 0
Table 153.Bit interpretation of bus timing 0 register (BTR0) (address 6)
The CAN core system clock is calculated as:
t
scl
= 2*t
clk
*(BRP+1)
where t
clk
is the system clock.
The sync jump width defines how many clock cycles (t
scl
) a bit period may be adjusted with by one
re-synchronization.
Table 152.Bit interpretation of clock divider register (CDR) (address 31)
Bit Name Description
CDR.7 CAN mode 1 - PeliCAN, 0 - BasiCAN
CDR.6 - unused (cbp bit of SJA1000)
CDR.5 - unused (rxinten bit of SJA1000)
CDR.4 - reserved
CDR.3 Clock off Disable the clkout output
CDR.2-0 Clock divisor Frequency selector
Bit Name Description
BT
R0.7-6 SJW Synchronization jump width
BTR0.5-0 BRP Baud rate prescaler
To Next Page
Loading...
Need help?
General
