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[31:12]: Address Tag (ATAG) - Contains the address of the data held in the cache line.
[3:0]: Valid (V) - When set, the corresponding sub-block of the cache line contains valid data. These bits are set when a
sub-block is filled due to a successful cache miss; a cache fill which results in a memory error will leave the valid
bit unset. V[0] corresponds to address 0 in the cache line, V[1] to address 1, V[2] to address 2 and V[3] to address 3.
4.5 Additional cache functionality
4.5.1 Cache flushing
Both instruction and data cache are flushed by executing the FLUSH instruction, or by writing to cer-
tain ASI address spaces. The instruction cache is also flushed by setting the FI bit in the cache control
register and the data cache is also flushed by setting the FD bit in the cache control register.
Cache flushing takes one cycle per cache line, during which the IU will not be halted, but during
which the caches are disabled. When the flush operation is completed, the cache will resume the state
(disabled, enabled or frozen) indicated in the cache control register. Diagnostic access to the cache is
not possible during a FLUSH operation and will cause a data exception (trap=0x09) if attempted.
4.5.2 Diagnostic cache access
Tags and data in the instruction and data cache can be accessed through ASI address space 0xC, 0xD,
0xE and 0xF by executing LDA and STA instructions. Address bits making up the cache offset will be
used to index the tag to be accessed while the least significant bits of the bits making up the address
tag will be used to index the cache set.
Diagnostic read of tags is possible by executing an LDA instruction with ASI=0xC for instruction
cache tags and ASI=0xE for data cache tags. A cache line and set are indexed by the address bits mak-
ing up the cache offset and the least significant bits of the address bits making up the address tag. Sim-
ilarly, the data sub-blocks may be read by executing an LDA instruction with ASI=0xD for instruction
cache data and ASI=0xF for data cache data. The sub-block to be read in the indexed cache line and
set is selected by A[4:2].
The tags can be directly written by executing a STA instruction with ASI=0xC for the instruction
cache tags and ASI=0xE for the data cache tags. The cache line and set are indexed by the address bits
making up the cache offset and the least significant bits of the address bits making up the address tag.
D[31:12] is written into the ATAG field (see figure 6 and figure 7) and the valid bits are written with
the D[7:0] of the write data. The data sub-blocks can be directly written by executing a STA instruc-
tion with ASI=0xD for the instruction cache data and ASI=0xF for the data cache data. The sub-block
to be read in the indexed cache line and set is selected by A[4:2].
In multi-way caches, the address of the tags and data of the ways are concatenated. The address of a
tag or data is thus:
ADDRESS = WAY & LINE & DATA & “00”
Examples: the tag for line 2 in way 1 of the 4x4 KiB data cache with 16 byte line would be:
A[13:12] = 1 (WAY)
A[11:5] = 2 (TAG)
=> TAG ADDRESS = 0x1040
The data of this line would be at addresses 0x1040 - 0x104C
4.5.3 Data Cache snooping
To keep the data cache synchronized with external memory, cache snooping can be enabled by setting
the DS bit in the cache control register. When enabled, the data cache monitors write accesses on the
AHB bus to cacheable locations. If an other AHB master writes to a cacheable location which is cur-
rently cached in the data cache, the corresponding cache line is marked as invalid.
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