GR712RC-UM, Jun 2017, Version 2.9 112 www.cobham.com/gaisler
GR712RC
16.4.10 Promiscuous mode
The GRSPW supports a promiscuous mode where all the data received is stored to the first DMA
channel enabled regardless of the node address and possible early EOPs/EEPs. This means that all
non-eop/eep N-Chars received will be stored to the DMA channel. The rxmaxlength register is still
checked and packets exceeding this size will be truncated.
If the RMAP handler is present, RMAP commands will still be handled by it when promiscuous mode
is enabled if the rmapen bit is set. If it is cleared, RMAP commands will also be stored to a DMA
channel.
16.5 Transmitter DMA channels
The transmitter DMA engine handles transmission of data from the DMA channels to the SpaceWire
network. Each receive channel has a corresponding transmit channel which means there can be up to
4 transmit channels. It is however only necessary to use a separate transmit channel for each receive
channel if there are also separate entities controlling the transmissions. The use of a single channel
with multiple controlling entities would cause them to corrupt each other’s transmissions. A single
channel is more efficient and should be used when possible.
Multiple transmit channels with pending transmissions are arbitrated in a round-robin fashion.
16.5.1 Basic functionality of a channel
A transmit DMA channel reads data from the AHB bus and stores them in the transmitter FIFO for
transmission on the SpaceWire network. Transmission is based on the same type of descriptors as for
the receiver and the descriptor table has the same alignment and size restrictions. When there are new
descriptors enabled the GRSPW reads them and transfer the amount data indicated.
16.5.2 Setting up the GRSPW for transmission
Four steps need to be performed before transmissions can be done with the GRSPW. First the link
interface must be enabled and started by writing the appropriate value to the ctrl register. Then the
address to the descriptor table needs to be written to the transmitter descriptor table address register
and one or more descriptors must also be enabled in the table. Finally, the txen bit in the DMA control
register is written with a one which triggers the transmission. These steps will be covered in more
detail in the next sections.
16.5.3 Enabling descriptors
The descriptor table address register works in the same way as the receiver’s corresponding register
which was covered in section 16.4. The maximum size is 1024 bytes as for the receiver but since the
descriptor size is 16 bytes the number of descriptors is 64.
To transmit packets one or more descriptors have to be initialized in memory which is done in the fol-
lowing way: The number of bytes to be transmitted and a pointer to the data has to be set. There are
two different length and address fields in the transmit descriptors because there are separate pointers
for header and data. If a length field is zero the corresponding part of a packet is skipped and if both
are zero no packet is sent. The maximum header length is 255 bytes and the maximum data length is
16 MiB - 1. When the pointer and length fields have been set the enable bit should be set to enable the
descriptor. This must always be done last. The other control bits must also be set before enabling the
descriptor.
The transmit descriptors are 16 bytes in size so the maximum number in a single table is 64. The dif-
ferent fields of the descriptor together with the memory offsets are shown in the tables below.
The HC bit should be set if RMAP CRC should be calculated and inserted for the header field and
correspondingly the DC bit should be set for the data field. This field is only used by the GRSPW
when the CRC logic is available. The header CRC will be calculated from the data fetched from the
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