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GR712RC
COBHAM GR712RC User Manual
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GR712RC-UM, Jun 2017
, Version 2.9
189
www.cobham.com/gaisler
GR712RC
26.4.1
Data formatting
When
in
the
decode
state,
each
candidate
codeblock
is
decoded
i
n
single
error
correction
mode
as
described hereafter
.
Figur
e 79.
Direct Memory
Access
ST
ART
INIT
init rx_w_ptr (lower bits)
fifo 50% fu
ll ?
CHECK
OVERFLOW
temp1 = rx_w_ptr
temp2 = rx_w_ptr +
temp3 = rx_r_ptr
temp2 >=
WRITE
burst of writes @ temp1
temp1 >=
RESET
temp1 = start addr+x
INCREMENT
temp1 =
temp1+x
UPDA
TE
rx_w_ptr
= temp1
set overflow-flag
temp3-offset ?
end addr?
# bytes received
N
Y
N
N
Y
Y
ST
ART
INIT
init rx_r_ptr & rx_w_ptr (ASR register)
CHECK
WA
I
T
temp1 = rx_w_ptr
temp2 = rx_r_ptr
temp1 =
temp2 ?
READ
read @ temp2
temp2 =
RESET
temp2 = start addr+y
INCREMENT
temp2 = temp2+y
TBD ms
end addr ?
N
N
Y
fifo 100% full ?
CHANNEL
RESET
Y
all data read ?
N
Y
Y
N
HARDW
ARE WRITE
SOFTW
ARE READ
Legend:
rx_w_ptr W
rite pointer
rx_r_ptr Read pointer
188
190
Table of Contents
Default Chapter
2
Table of Contents
2
1 Introduction
7
Scope
7
GR712RC Architecture
7
Memory Map
8
Interrupts
9
GRLIB IP Cores
9
References
10
Errata
11
Document Revision History
18
2 Signals and I/O Switch Matrix
22
3 Clocking
32
System Clock
32
Spacewire Clock
32
Mil-Std-1553
33
Telemetry
33
Telecommand
33
Obsolete
33
Slink
33
SDRAM Clock
34
Clock Gating Unit
34
Test Mode Clocking
35
4 LEON3FT - High-Performance SPARC V8 32-Bit Processor
36
Overview
36
LEON3 Integer Unit
37
Instruction Cache
44
Data Cache
45
Additional Cache Functionality
46
Memory Management Unit
48
Floating-Point Unit
50
Error Detection and Correction
50
Signal Definitions
52
5 Fault Tolerant Memory Controller
53
Overview
53
PROM Access
54
Memory Mapped IO
56
SRAM Access
57
8-Bit PROM and SRAM Access
58
8- Bit I/O Access
59
Burst Cycles
59
SDRAM Access
59
Refresh
60
Memory EDAC
62
Bus Ready Signalling
64
External Bus Errors
65
Read Strobe
66
Registers
66
Signal Definitions
69
6 On-Chip Memory with EDAC Protection
70
Overview
70
Operation
70
Registers
71
7 AHB Status Registers
72
Overview
72
Operation
72
Registers
72
8 Multiprocessor Interrupt Controller
73
Overview
73
Operation
73
Registers
75
9 Hardware Debug Support Unit
78
Overview
78
Operation
78
AHB Trace Buffer
79
Instruction Trace Buffer
80
DSU Memory Map
81
DSU Registers
82
10 JTAG Debug Interface
85
Overview
85
Operation
85
Registers
86
Signal Definitions
86
11 General Purpose Timer Unit
87
Overview
87
Operation
87
Registers
88
Signal Definitions
89
12 General Purpose Timer Unit with Time Latch Capability
90
Overview
90
Operation
90
Registers
91
13 General Purpose Register
93
Operation
93
Registers
93
14 General Purpose I/O Port
94
Overview
94
Operation
94
Registers
96
Signal Definitions
97
15 UART Serial Interface
98
Overview
98
Operation
98
Baud-Rate Generation
99
Loop Back Mode
99
FIFO Debug Mode
100
Interrupt Generation
100
Registers
100
Signal Definitions
102
16 Spacewire Interface with RMAP Support
103
16.2.1 Overview
103
Operation
103
Link Interface
104
Receiver DMA Channels
106
Transmitter DMA Channels
112
Rmap
115
AMBA Interface
120
Spacewire Clock Generation
121
Registers
122
16.10 Signal Definitions
127
17 Ethernet Media Access Controller (MAC)
128
Overview
128
Operation
128
Tx DMA Interface
129
Rx DMA Interface
130
MDIO Interface
132
Reduced Media Independent Interfaces (RMII)
132
Registers
132
Signal Definitions
135
18 CAN Interface
136
Overview
136
CAN Controller Overview
136
AHB Interface
136
Basiccan Mode
137
Pelican Mode
141
Common Registers
151
Design Considerations
152
Signal Definitions
152
19 Obsolete
153
Signal Definitions
153
20 CAN Bus Multiplexor
154
Overview
154
Operation
154
Registers
154
21 Mil-Std-1553B Bc/Rt/Bm
155
Overview
155
AHB Interface
156
1553 Clock Generation
156
Registers
158
Signal Definitions
159
22 I2C-Master
160
Overview
160
Operation
160
Registers
163
Signal Definitions
165
23 SPI Controller
166
Overview
166
Operation
166
Registers
168
Signal Definitions
171
24 SLINK Serial Bus Based Real-Time Network Master
172
Overview
172
Operation
172
Registers
175
Signal Definitions
179
25 ASCS Controller
180
Overview
180
Operation
180
Registers
181
Signal Definitions
183
26 GRTC - Telecommand Decoder
184
Overview
184
Data Formats
185
Coding Layer (CL)
186
Transmission
188
Relationship between Buffers and Fifos
191
Command Link Control Word Interface (CLCW)
193
Configuration Interface (AMBA AHB Slave)
193
Miscellaneous
194
Registers
195
26.10 Signal Definitions
202
27 GRTM - CCSDS Telemetry Encoder
203
Overview
203
References
204
Layers
205
Data Link Protocol Sub-Layer
206
Synchronization and Channel Coding Sub-Layer
208
Physical Layer
211
Connectivity
213
Operation
214
Registers
217
27.10 Signal Definitions
221
28 Clock Gating Unit
222
Overview
222
Operation
222
Registers
223
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COBHAM GR712RC Specifications
General
Brand
COBHAM
Model
GR712RC
Category
Computer Hardware
Language
English
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