GR712RC-UM, Jun 2017, Version 2.9 174 www.cobham.com/gaisler
GR712RC
Software should only change the base address registers when the SEQUENCE Active (SA) bit in the
Status register is zero. The core starts processing the elements of array A at the address set in the
Array Base Address register and writes responses to the B array. The response to an operation
described by an element at A[i] is placed at position B[i]. The core maintains a queue of SEQUENCE
operations which enables it to start operation A[i+1] in the SYNC cycle after the response to opera-
tion A[i] has been received.
When SLEN+1 elements in the A array have been processed and corresponding responses have been
written to the B array, the core will clear the Control register’s SEQUENCE Enable (SE) bit and set
SEQUENCE Completed (SC) in the Status register. The SEQUENCE Completed bit can be used as
an interrupt source by setting the corresponding bit in the Mask register.
A SEQUENCE may be prematurely terminated by an error event or by software intervention. If the
core receives an ERROR response to a transfer on the AMBA AHB bus the AMBA ERROR (AERR)
bit in the status register will be set and the SEQUENCE Completed (SC) bit will not be set.
If software aborts a SEQUENCE operation by setting the Abort SEQUENCE (AS) bit in the Control
register the core will write back the currently completed operations and will then clear the Control
register’s SE and SA bits. If the core completed all SLEN operations the SEQUENCE Completed
(SC) bit will be set, otherwise the Sequence Aborted (SA) bit will be set. If the Sequence Aborted bit
is set, the SEQUENCE Index (SI) field in the Status register can be used to determine the number suc-
cessful transfers that were written back to the B array. If a SEQUENCE is aborted while a slave is pre-
paring a response, and the response arrives after the abort procedure has finished, the last response
will be interpreted as an unsolicited request and placed in the receive queue. The core will clear the
Abort SEQUENCE (AS) bit when the SEQUENCE has been aborted and all the completed operations
have been written back to memory.
The core is also capable of receive-only SEQUENCE operation. When the SEQUENCE Receive
Only (SRO) bit is set in the Control register the core will not access the elements in the A array and
will, when the SEQUENCE Enable bit is set, store incoming data words with a channel matching the
SEQUENCE channel number into the B array. All other behavior is identical to a normal
SEQUENCE operation.
24.2.4 MASTER-WORD-SEND, SLAVE-WORD-SEND and INTERRUPT requests
Single READ/WRITE operations of data transfer type MASTER-WORD-SEND are performed by
writing to the core’s Transmit register. This register may only be written when the Status register bit
Transmit Not Full (TNF) is set. Writes to the transmit register when the TNF bit is not set may over-
write a previously written value.
The core does not distinguish between the three transfer types MASTER-WORD-SEND, INTER-
RUPT and SLAVE-WORD-SEND. All received words, that do not belong to a ongoing SEQUENCE
operation, are placed in the receive queue. Software can detect and identify the type of incoming
words by monitoring the Receive Not Empty (RNE) and SLINK Received (SRX) bits in the status
field. Both bits can be used as interrupt sources. It is recommended that software makes use of
Receive Not Empty as an interrupt source and identifies the transfer type of the word by reading the
Receive register and examining the appropriate fields. Even if SLINK Received is set and used as the
interrupt source, software must never read the Receive register unless the Receive Not Empty bit is
set.
Note that if the core receives a word that has a channel field value that matches the value of
SEQUENCE Channel Number (SCN) and there is no ongoing SEQUENCE operation the core will
regard this to be an unsolicited request and will place the word in the receive queue.
24.2.5 Parity and Parity Error
Parity is calculated on bits 1 to 24 of both received and sent SLINK words. The Control register bit
Parity (PAR) determines if the core uses odd or even parity. If the core detects a parity error, the
received word is discarded and the Parity Error (PERR) bit in the status register is set. If the Parity
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