GR712RC-UM, Jun 2017, Version 2.9 173 www.cobham.com/gaisler
GR712RC
Core operation for the first three types of transfers is described in section 24.2.4 and SEQUENCE
operation is described in section 24.2.3. Conflicts on the bus are resolved by the slaves, the master
performs no arbitration nor collision detection.
The core considers the data on the SDI line to be a SLINK word if bit 21 of the data word is ‘0’.
24.2.2 Receive and transmit queues
The core uses receive and transmit queues to guarantee that it is able to transmit word k+1 directly
after word k has been sent and that word m+1 can be received directly after word m. The core also has
receive and transmit queues for SEQUENCE transfers, this section describes the queues used for
MASTER-WORD-SEND, INTERRUPT and SLAVE-WORD-SEND transfers.
The receive and transmit queues are implemented as FIFOs with room for three SLINK data words
each. The back of the transmit queue is the Transmit register and the front of the receive queue is the
Receive register. Software can monitor the status of these queues via the Transmit Not Full (TNF) and
Receive Not Empty (RNE) bits in the status register. The core can be configured to generate interrupts
when these bits transition to one.
If the receive queue is full when a word is received the core will discard the received word and assert
the Status register bit Receive Overflow (ROV). This is a critical error since the master system must
guarantee that words can be received without delay.
24.2.3 SEQUENCE operations
During a SEQUENCE of operations the core performs READ/WRITE operations described by an in-
memory array A. Responses to these operations are written back to an array named B. The core exe-
cutes one operation and waits for the response before executing the operation described by the next
element in A. To determine if a received word is a response to a SEQUENCE operation the core com-
pares the received word’s channel field to the value of the Sequence Channel Number (SCN) field in
the Control register. If the values match, the received word is considered to be a response to the cur-
rent operation and the core will execute the next pending SEQUENCE operation in the next SYNC
cycle. If the core has pending MASTER-WORD-SEND transfers it will interleave these among the
SEQUENCE operations. However, SEQUENCE operations have higher priority.
Software initiates a SEQUENCE transfer by allocating room for both arrays and filling array A with
words that match the format of the Transmit register. The base address of this array is then written to
the Array A Base Address register. The base address of array B is written to the Array B Base Address
Register. Software enables processing of the SEQUENCE operations by setting the SEQUENCE
Enable (SE) bit and initializing the SEQUENCE Length (SLEN) and SEQUENCE Channel Number
(SCN) fields in the Control register.
Table 182. Data word format for master to slaves
24 23 17 16 1 0 SYNC
RD/WR
CHAN. NO DATA / ADDRESS PARITY X
Table 183. Data word format for slave to master
24 23 22 21 20 17 16 1 0 SYNC
Hi-Z SLAVE # 0 CHAN. NO DATA PARITY 1
Table 184. NULL word sent by master
24 23 17 16 1 0 SYNC
0 0000000 0000000000000000 1 X
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