COBHAM GR712RC - 8.3.3 Interrupt force register, processor 0; 8.3.4 Interrupt clear register; 8.3.5 Multiprocessor status register; 8.3.6 Processor interrupt mask register

GR712RC-UM, Jun 2017, Version 2.9 76 www.cobham.com/gaisler
GR712RC
8.3.3 Interrupt force register, processor 0
Figure 35. Processor interrupt force register
031
0
1
15
16
IF[15:1]
“000...0”
[31:16] Reserved.
[15:1] Interrupt Force n (IF[n]): Force interrupt no. n. The resulting IF[n] is the value of the written value to IF[n].
[0] Reserved.
8.3.4 Interrupt clear register
Figure 36. Interrupt clear register
031
“000...0”
0
1
15
16
IC[15:1]
[31:16] Reserved.
[15:1] Interrupt Clear n (IC[n]): Writing ‘1’ to ICn will clear interrupt n. Write only, reads zeros.
[0] Reserved.
8.3.5 Multiprocessor status register
Figure 37. Multiprocessor status register
031
“000...0”
15
STATUS[15:0]
16
28
NCPU
20 19
EIRQ
27
26
BA
[31:28] NCPU. Number of CPU’s in the system -1. Read only. Fixed to 1, i.e. 2 processors.
[27] Broadcast Available (BA). Set to ‘1’.
[19:16] EIRQ. Interrupt number (1 - 15) used for extended interrupts. Read only. Fixed to 12.
[15:1] Power-down status of CPU [n]: reads ‘1’ = power-down, ‘0’ = running. Write to start processor n: ‘1’=to start,
‘0=has no effect.
8.3.6 Processor interrupt mask register
Figure 38. Processor interrupt mask register
031
EIM[31:16]
0
1
15
16
IM[15:1]
[31:16] Interrupt mask for extended interrupts
[15:1] Interrupt Mask n (IM[n]): If IMn = 0 the interrupt n is masked, otherwise it is enabled.
[0] Reserved.