COBHAM GR712RC - 8.3.7 Broadcast register; 8.3.8 Processor interrupt force register; 8.3.9 Extended interrupt identification register

GR712RC-UM, Jun 2017, Version 2.9 77 www.cobham.com/gaisler
GR712RC
8.3.7 Broadcast register
Figure 39. Broadcast register
031
“000...0”
0
1
15
16
IM[15:1]
[31:16] Reserved.
[15:1] Broadcast Mask n (BM[n]): If BMn = 1 the interrupt n is broadcasted (written to the Force Register of all CPUs),
otherwise standard semantic applies (Pending Register).
[0] Reserved.
8.3.8 Processor
Figure 40. Processor interrupt force register
031
IFC[15:1]
0
1
15
16
IF[15:1]
17
0
interrupt force register
[31:17] Interrupt Force Clear n (IFC[n]). Write only, reads zeros.
[15:1] Interrupt Force n (IF[n]): Force interrupt no. n. The resulting IF[n] is a combination of the written value to IF[n] and
the written value of IFC[n] and the previous state of IF[n].
[0] Reserved.
8.3.9 Extended interrupt identification register
Figure 41. Extended interrupt identification register
031
4
5
EID[4:0]
[4:0] ID (16 - 31) of the acknowledged extended interrupt. Read only.