COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 68 www.cobham.com/gaisler
GR712RC
5.14.3 Memory configuration register 3 (MCFG3)
MCFG3 controls the SDRAM refresh counter and memory EDAC.
The period between each AUTO-REFRESH command is calculated as follows:
t
REFRESH
= ((reload value) + 1) / SYSCLK
29: 27 SDRAM TRFC parameter (SDRAM TRFC) - t
RFC
will be equal to 3+field-value system clocks.
26 SDRAM TCAS parameter (TCAS) - Selects 2 or 3 cycle CAS delay (0/1). When changed, a LOAD-
COMMAND-REGISTER command must be issued at the same time. Also sets RAS/CAS delay
(t
RCD).
25: 23 SDRAM bank size (SDRAM BANKSZ) - Sets the bank size for SDRAM chip selects (“000”=4MiB,
“001”=8MiB, “010”=16MiB.... “111”=512MiB).
22: 21 SDRAM column size (SDRAM COLSZ) - “00”=256, “01”=512, “10”=1024, “11”=2048 except
when bit[25:23]=“111” then “11”=4096
20: 19 SDRAM command (SDRAM CMD) - Writing a non-zero value will generate a SDRAM command.
“01”=PRECHARGE, “10”=AUTO-REFRESH, “11”=LOAD-COMMAND-REGISTER. The field is
reset after the command has been executed.
18 0
17 0
16: 15 RESERVED
14 SDRAM enable (SE) - Enables the SDRAM controller
13 SRAM disable (SI) - Disables accesses to SRAM bank if bit 14 (SE) is set to ‘1’.
12: 9 RAM bank size (RAM BANK SIZE) - Sets the size of each RAM bank ("0000"=8KiB,
"0001"=16KiB, "0010"=32KiB, "0011"=64KiB,.., "1011"=16MiB) (i.e. 8KiB * 2**RAM BANK
SIZE).
8 RESERVED
70
6 Read-modify-write enable (RMW) - Enables read-modify-write cycles for sub-word writes 32-bit
RAM areas. NOTE: must be set if RAM area is 32-bit.
5: 4 RAM width (RAM WIDTH) - Sets the data width of the RAM area (“00”=8, “1X”=32).
3: 2 RAM write waitstates (RAM WRITE WS) - Sets the number of wait states for RAM write cycles
(“00”=0, “01”=1, “10”=2, “11”=3).
1: 0 RAM read waitstates (RAM READ WS) - Sets the number of wait states for RAM read cycles
(“00”=0, “01”=1, “10”=2, “11”=3).
Table 31. Memory configuration register 3
31 28 27 26
RESERVED RSE ME SDRAM REFRESH COUNTER
121110987 0
WB RB RE PE TCB
31: 29 RESERVED
28 Reed-Solomon EDAC enable (RSE) - if set, will enable Reed-Solomon protection of SDRAM area
when implemented
27 1
26: 12 SDRAM refresh counter reload value (SDRAM REFRESH COUNTER)
11 EDAC diagnostic write bypass (WB) - Enables EDAC write bypass.
10 EDAC diagnostic read bypass (RB) - Enables EDAC read bypass.
9 RAM EDAC enable (RE) - Enable EDAC checking of the RAM area (including SDRAM).
8 PROM EDAC enable (PE) - Enable EDAC checking of the PROM area. Ar reset, this bit is initial-
ized with the value of SWMX[4].
7: 0 Test checkbits (TCB) - This field replaces the normal checkbits during write cycles when WB is set.
It is also loaded with the memory checkbits during read cycles when RB is set.
Table 30. Memory configuration register 2

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English