COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 215 www.cobham.com/gaisler
GR712RC
in this section.
To enable a descriptor the enable (EN) bit should be set and after this is done, the descriptor should
not be touched until the enable bit has been cleared by the core.
27.8.3 Starting transmissions
Enabling a descriptor is not enough to start a transmission. A pointer to the memory area holding the
descriptors must first be set in the core. This is done in the transmitter descriptor pointer register. The
address must be aligned to a 1 KiB boundary. Bits 31 to 10 hold the base address of descriptor area
while bits 9 to 3 form a pointer to an individual descriptor.The first descriptor should be located at the
base address and when it has been used by the core, the pointer field is incremented by 8 to point at
the next descriptor. The pointer will automatically wrap back to zero when the next 1 KiB boundary
has been reached (the descriptor at address offset 0x3F8 has been used). The WR bit in the descriptors
can be set to make the pointer wrap back to zero before the 1 KiB boundary.
The pointer field has also been made writable for maximum flexibility but care should be taken when
writing to the descriptor pointer register. It should never be touched when a transmission is active.
The final step to activate the transmission is to set the transmit enable bit in the DMA control register.
This tells the core that there are more active descriptors in the descriptor table. This bit should always
be set when new descriptors are enabled, even if transmissions are already active. The descriptors
must always be enabled before the transmit enable bit is set.
Table 223. GRTM transmit descriptor word 0 (address offset 0x0)
31 16151413109876543210
RESERVED UE TS 0000 VCE MCB - OCFB FHECB - FECFB IE WR EN
31: 16 RESERVED
15 Underrun Error (UE) - underrun occurred while transmitting frame (status bit only)
14 Time Strobe (TS) - generate a time strobe for this frame
13: 10 RESERVED
9 Virtual Channel Counter Enable (VCE) - enable virtual channel counter generation (using the Idle
Frame virtual channel counter)
8 Master Channel Counter Bypass (MCB) - bypass master channel counter generation (TM only)
7RESERVED
6 Operational Control Field Bypass (OCFB) - bypass operational control field generation
5 Frame Error Header Control Bypass (FECHB) - bypass frame error header control generation (AOS)
4RESERVED
3 Frame Error Control Field Bypass (FECFB) - bypass frame error control field generation
2 Interrupt Enable (IE) - an interrupt will be generated when the frame from this descriptor has been
sent provided that the transmitter interrupt enable bit in the control register is set. The interrupt is
generated regardless if the frame was transmitted successfully or if it terminated with an error.
1 Wrap (WR) - Set to one to make the descriptor pointer wrap to zero after this descriptor has been
used. If this bit is not set the pointer will increment by 8. The pointer automatically wraps to zero
when the 1 KiB boundary of the descriptor table is reached.
0 Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor
fields.
Table 224. GRTM transmit descriptor word 1 (address offset 0x4)
31 210
ADDRESS RES
31: 2 Address (ADDRESS) - Pointer to the buffer area from where the packet data will be loaded.
1: 0 RESERVED

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English