COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 216 www.cobham.com/gaisler
GR712RC
27.8.4 Descriptor handling after transmission
When a transmission of a frame has finished, status is written to the first word in the corresponding
descriptor. The Underrun Error bit is set if the FIFO became empty before the frame was completely
transmitted. The other bits in the first descriptor word are set to zero after transmission while the sec-
ond word is left untouched. The enable bit should be used as the indicator when a descriptor can be
used again, which is when it has been cleared by the core.
There are multiple bits in the DMA status register that hold transmission status.
The Transmitter Interrupt (TI) bit is set each time a DMA transmission of a transfer frame ended suc-
cessfully. An interrupt is generated for transfer frames for which the Interrupt Enable (IE) was set in
the descriptor. The interrupt is maskable with the Interrupt Enable (IE) bit in the control register.
If a DMA transmission of a transfer frame ends with an underrun error, the Underrun Error (UE) bit in
the descriptor will be written to 1 and the Enable (EN) bit will be written to 0; the Transmitter Error
(TE) bit in the DMA status register will be set and the Enable (EN) bit in the DMA control register
will be cleared; an interrupt will be generated if not masked with the Interrupt Enable (IE) bit in the
control register. The Telemetry Encoder will continue sending idle transfer frames after the failed
transfer frame. The Telemetry Encoder requires a complete reset after an underrun error before new
user transfer frames can be sent.
The Transmitter AMBA error (TA) bit is set when an AMBA AHB error was encountered either when
reading a descriptor or when reading transfer frame data. Any active transmissions were aborted and
the DMA channel was disabled. It is recommended that the Telemetry Encoder is reset after an
AMBA AHB error. The interrupt is maskable with the Interrupt Enable (IE) bit in the control register.
The Transfer Frame Sent (TFS) bit is set whenever a transfer frame has been sent, independently if it
was sent via the DMA interface or generated by the core. The interrupt is maskable with the Transfer
Frame Interrupt Enable (TFIE) bit in the control register.
The Transfer Frame Failure (TFF) bit is set whenever a transfer frame has failed for other reasons,
such as when Idle Frame generation is not enabled and no user Transfer Frame is ready for transmis-
sion, independently if it was sent via the DMA interface or generated by the core. The interrupt is
maskable with the Transfer Frame Interrupt Enable (TFIE) bit in the control register.
The Transfer Frame Ongoing (TFO) bit is set when DMA transfers are enabled, and is not cleared
until all DMA induced transfer frames have been transmitted after DMA transfers are disabled.
27.8.5 Interrupts
The Transfer Frame Sent (TFS) and Transfer Frame Failure (TFF) interrupts are maskable with the
Transfer Frame Interrupt Enable (TFIE) bit in the DMA control register, and can be observed via the
DMA status register.
The Transmitter Interrupt (TI), Transmitter Error (TE) and Transmitter AMBA Error (TA) interrupts
are maskable with the Interrupt Enable (IE) bit in the DMA control register, and can be observed via
the DMA status register.
The Time Strobe Interrupt (TSI) is maskable with the Transfer Frame Interrupt Enable (TFIE) bit in
the DMA control register.
All interrupts except Time Strobe Interrupt (TSI) are output on interrupt number 29.
The Time Strobe Interrupt (TSI) is output on interrupt number 30.

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English