COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 167 www.cobham.com/gaisler
GR712RC
23.2.2 Receive and transmit queues
The core’s transmit queue consists of the transmit register and the transmit FIFO. The receive queue
consists of the receive register and the receive FIFO. The total number of words that can exist in each
queue is thus the FIFO depth plus one. When the core has one or more free slots in the transmit queue
it will assert the Not full (NF) bit in the event register. Software may only write to the transmit register
when this bit is asserted. When the core has received a word, as defined by word length (LEN) in the
Mode register, it will place the data in the receive queue. When the receive queue has one or more ele-
ments stored the Event register bit Not empty (NE) will be asserted. The receive register will only
contain valid data if the Not empty bit is asserted and software should not access the receive register
unless this bit is set. If the receive queue is full and the core receives a new word, an overrun condi-
tion will occur. The received data will be discarded and the Overrun (OV) bit in the Event register will
be set.
23.2.3 Clock generation
The core only generates the clock in master mode, the generated frequency depends on the system
clock frequency and the Mode register fields DIV16, FACT, and PM. Without DIV16 the SPICLK
frequency is:
With DIV16 enabled the frequency of SPICLK is derived through:
Figure 74. SPI transfer of byte 0x55 in all modes
SPICLK
SPIMOSI
CPOL = 0
CPHA = 0
CPHA = 1
CPOL = 1
CPHA = 0
CPHA = 1
Mode 0
Mode 1
Mode 2
Mode 3
SPICLK
SPIMOSI
SPICLK
SPIMOSI
SPICLK
SPIMOSI
SCKFrequency
AMBAclockfrequency
42FACT–PM 1+
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COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English