COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 131 www.cobham.com/gaisler
GR712RC
17.4.2 Starting reception
Enabling a descriptor is not enough to start reception. A pointer to the memory area holding the
descriptors must first be set in the GRETH. This is done in the receiver descriptor pointer register. The
address must be aligned to a 1 kB boundary. Bits 31 to 10 hold the base address of descriptor area
while bits 9 to 3 form a pointer to an individual descriptor. The first descriptor should be located at the
base address and when it has been used by the GRETH the pointer field is incremented by 8 to point at
the next descriptor. The pointer will automatically wrap back to zero when the next 1 kB boundary has
been reached (the descriptor at address offset 0x3F8 has been used). The WR bit in the descriptors can
be set to make the pointer wrap back to zero before the 1 kB boundary.
The pointer field has also been made writable for maximum flexibility but care should be taken when
writing to the descriptor pointer register. It should never be touched when reception is active.
The final step to activate reception is to set the receiver enable bit in the control register. This will
make the GRETH read the first descriptor and wait for an incoming packet.
17.4.3 Descriptor handling after reception
The GRETH indicates a completed reception by clearing the descriptor enable bit. The other control
bits (WR, IE) are also cleared. The number of received bytes is shown in the length field. The parts of
the Ethernet frame stored are the destination address, source address, type and data fields. Bits 17-14
in the first descriptor word are status bits indicating different receive errors. All four bits are zero after
a reception without errors. The status bits are described in table 108.
Packets arriving that are smaller than the minimum Ethernet size of 64 B are not considered as a
reception and are discarded. The current receive descriptor will be left untouched an used for the first
packet arriving with an accepted size. The TS bit in the status register is set each time this event
occurs.
If a packet is received with an address not accepted by the MAC, the IA status register bit will be set.
Packets larger than maximum size cause the FT bit in the receive descriptor to be set. The length field
is not guaranteed to hold the correct value of received bytes. The counting stops after the word con-
taining the last byte up to the maximum size limit has been written to memory.
16 CRC error (CE) - A CRC error was detected in this frame.
15 Frame too long (FT) - A frame larger than the maximum size was received. The excessive part
was truncated.
14 Alignment error (AE) - An odd number of nibbles were received.
13 Interrupt Enable (IE) - Enable Interrupts. An interrupt will be generated when a packet has been
received to this descriptor provided that the receiver interrupt enable bit in the control register is set.
The interrupt is generated regardless if the packet was received successfully or if it terminated with
an error.
12 Wrap (WR) - Set to one to make the descriptor pointer wrap to zero after this descriptor has been
used. If this bit is not set the pointer will increment by 8. The pointer automatically wraps to zero
when the 1 kB boundary of the descriptor table is reached.
11 Enable (EN) - Set to one to enable the descriptor. Should always be set last of all the descriptor
fields.
10: 0 LENGTH - The number of bytes received to this descriptor.
Table 109. GRETH receive descriptor word 1 (address offset 0x4)
31 210
ADDRESS RES
31: 2 Address (ADDRESS) - Pointer to the buffer area from where the packet data will be loaded.
1: 0 RESERVED
Table 108. GRETH receive descriptor word 0 (address offset 0x0)

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English