GR712RC-UM, Jun 2017, Version 2.9 138 www.cobham.com/gaisler
GR712RC
18.4.2 Control register
The control register contains interrupt enable bits as well as the reset request bit.
18.4.3 Command register
Writing a one to the corresponding bit in this register initiates an action supported by the core.
A transmission is started by writing 1 to CMR.0. It can only be aborted by writing 1 to CMR.1 and
only if the transfer has not yet started. If the transmission has started it will not be aborted when set-
ting CMR.1 but it will not be retransmitted if an error occurs.
Giving the Release receive buffer command should be done after reading the contents of the receive
buffer in order to release this memory. If there is another message waiting in the FIFO a new receive
interrupt will be generated (if enabled) and the receive buffer status bit will be set again.
To clear the Data overrun status bit CMR.3 must be written with 1.
Table 122.Bit interpretation of control register (CR) (address 0)
Bit Name Description
CR.7 - reserved
CR.6 - reserved
CR.5 - reserved
CR.4 Overrun Interrupt Enable 1 - enabled, 0 - disabled
CR.3 Error Interrupt Enable 1 - enabled, 0 - disabled
CR.2 Transmit Interrupt Enable 1 - enabled, 0 - disabled
CR.1 Receive Interrupt Enable 1 - enabled, 0 - disabled
CR.0 Reset request Writing 1 to this bit aborts any ongoing transfer and enters reset mode. Writ-
ing 0 returns to operating mode.
Table 123.Bit interpretation of command register (CMR) (address 1)
Bit Name Description
CMR.7 - reserved
CMR.6 - reserved
CMR.5 - reserved
CMR.4 - not used (go to sleep in SJA1000 core)
CMR.3 Clear data overrun Clear the data overrun status bit
CMR.2 Release receive buffer Free the current receive buffer for new reception
CMR.1 Abort transmission Aborts a not yet started transmission.
CMR.0 Transmission request Starts the transfer of the message in the TX buffer
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