GR712RC-UM, Jun 2017, Version 2.9 161 www.cobham.com/gaisler
GR712RC
If the data bitrate is too high for a slave device, it may stretch the clock period by keeping I2CSCL
low after the master has driven I2CSCL low.
22.2.2 Clock generation
The core uses the prescale register to determine the frequency of the I2CSCL clock line and of the
5*I2CSCL clock that the core uses internally. To calculate the prescale value use the formula:
The SCLfrequency is 100 kHz for Standard-mode operation (100 kb/s) and 400 kHz for Fast mode
operation. To use the core in Standard-mode in a system with a 60 MHz clock driving the AMBA bus
the required prescale value is:
Note that the prescale register should only be changed when the core is disabled. The minimum rec-
ommended prescale value is 3 due to synchronization issues. Lower values may cause the master to
violate I
2
C timing requirements. This limits the minimum system frequency to 2 MHz for operation in
Standard-mode.
22.2.3 Interrupts
The core generates interrupt 28. The interrupt can be enabled by setting the EN bit in the control reg-
ister.
22.2.4 Software operational model
The core is initialized by writing an appropriate value to the clock prescale register and then setting
the enable (EN) bit in the control register. Interrupts are enabled via the interrupt enable (IEN) bit in
the control register.
To write a byte to a slave the I
2
C-master must generate a START condition and send the slave address
with the R/W
bit set to ‘0’. After the slave has acknowledged the address, the master transmits the
Figure 72. Complete I
2
C data transfer
START MSB
LSB R/W ACK
I2CSCL
I2CSDA
continued...
Slave address
1 2 3 4 5 6 7 8 9
MSB
LSB ACK STOP
I2CSCL
I2CSDA
Data
1 2 3 4 5 6 7 8 9
Prescale
AMBAclockfrequency
5 SCLfrequency
----------------------------------------------------------
1–=
Prescale
60Mhz
5 100kHz
--------------------------
1– 119 0x77===
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