COBHAM GR712RC User Manual

GR712RC-UM, Jun 2017, Version 2.9 162 www.cobham.com/gaisler
GR712RC
data, waits for an acknowledge and generates a STOP condition. The sequence below instructs the
core to perform a write:
1. Left-shift the I
2
C-device address one position and write the result to the transmit register. The
least significant bit of the transmit register (R/W
) is set to ‘0’.
2. Generate START condition and send contents of transmit register by setting the STA and WR
bits in the command register.
3. Wait for interrupt, or for TIP bit in the status register to go low.
4. Read RxACK bit in status register. If RxACK is low the slave has acknowledged the transfer,
proceed to step 5. If RxACK is set the device did not acknowledge the transfer, go to step 1.
5. Write the slave-data to the transmit register.
6. Send the data to the slave and generate a stop condition by setting STO and WR in the com-
mand register.
7. Wait for interrupt, or for TIP bit in the status register to go low.
8. Verify that the slave has acknowledged the data by reading the RxACK bit in the status regis-
ter. RxACK should not be set.
To read a byte from an I
2
C-connected memory much of the sequence above is repeated. The data writ-
ten in this case is the memory location on the I
2
C slave. After the address has been written the master
generates a repeated START condition and reads the data from the slave. The sequence that software
should perform to read from a memory device:
1. Left-shift the I
2
C-device address one position and write the result to the transmit register. The
least significant bit of the transmit register (R/W) is set to ‘0’.
2. Generate START condition and send contents of transmit register by setting the STA and WR
bits in the command register.
3. Wait for interrupt or for TIP bit in the status register to go low.
4. Read RxACK bit in status register. If RxACK is low the slave has acknowledged the transfer,
proceed to step 5. If RxACK is set the device did not acknowledge the transfer, go to step 1.
5. Write the memory location to be read from the slave to the transmit register.
6. Set the WR bit in the command register. Note that a STOP condition is not generated here.
7. Wait for interrupt, or for TIP bit in the status register to go low.
8. Read RxACK bit in the status register. RxACK should be low.
9. Address the I
2
C-slave again by writing its left-shifted address into the transmit register. Set the
least significant bit of the transmit register (R/W) to ‘1’ to read from the slave.
10. Set the STA and WR bits in the command register to generate a repeated START condition.
11. Wait for interrupt, or for TIP bit in the status register to go low.
12. Read RxACK bit in the status register. The slave should acknowledge the transfer.
13. Prepare to receive the data read from the I
2
C-connected memory. Set bits RD, ACK and STO
on the command register. Setting the ACK bit NAKs the received data and signifies the end of
the transfer.
14. Wait for interrupt, or for TIP in the status register to go low.
15. The received data can now be read from the receive register.
To perform sequential reads the master can iterate over steps 13 - 15 by not setting the ACK and STO
bits in step 13. To end the sequential reads the ACK and STO bits are set. Consult the documentation
of the I
2
C-slave to see if sequential reads are supported.

COBHAM GR712RC Specifications

General

Brand	COBHAM
Model	GR712RC
Category	Computer Hardware
Language	English